Merge pull request #158 from garytwong/fpc-iii
Add FPC-III board support.
This commit is contained in:
enjoy-digital
GitHub
commit
4eb5533040
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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import os
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clock
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("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
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# LEDs
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("user_led", 0, Pins("N16"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 1, Pins("P20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 2, Pins("R20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 3, Pins("N20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 4, Pins("U20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 5, Pins("M20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 6, Pins("T20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 7, Pins("D6"), IOStandard("LVCMOS33"), Misc( "OPENDRAIN=ON" ) ),
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# Serial
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#("serial", 0,
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# Subsignal("rx", Pins("N2"), IOStandard("LVCMOS33")),
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# Subsignal("tx", Pins("M1"), IOStandard("LVCMOS33"))),
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# USB FIFO
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("usb_fifo", 0,
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Subsignal( "data", Pins( "N2 M1 M3 L1 L2 K1 K2 J1" ) ),
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Subsignal( "rxf_n", Pins( "H1" ) ),
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Subsignal( "txe_n", Pins( "H2" ) ),
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Subsignal( "rd_n", Pins( "G1" ) ),
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Subsignal( "wr_n", Pins( "G2" ) ),
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Subsignal( "siwua", Pins( "F1" ) )
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("W2"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("V2"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")),
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("clk", Pins("A9")),
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Subsignal("mosi", Pins("E9"), Misc("PULLMODE=UP")),
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Subsignal("cs_n", Pins("B8"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins("D9"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("clk", Pins("A9")),
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Subsignal("cmd", Pins("E9"), Misc("PULLMODE=UP")),
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Subsignal("data", Pins("D9 B9 C8 B8"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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# USB ULPI
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("ulpi", 0,
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Subsignal("clk", Pins("C6")),
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Subsignal("stp", Pins("D7")),
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Subsignal("dir", Pins("A7")),
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Subsignal("nxt", Pins("C7")),
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Subsignal("reset", Pins("D8")),
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Subsignal("data", Pins("A5 B5 A4 B4 A3 B3 A2 B2")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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("dram_vtt_en", 0, Pins( "M19" ), IOStandard( "LVCMOS15" ), Misc( "OPENDRAIN=ON" ) ),
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("ddram", 0,
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Subsignal( "a", Pins( "E18 H16 D18 L16 H17 E17 G18 C18 "
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"G16 D17 J16 F18 J17 F16 F17" ),
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IOStandard( "SSTL15_I" ) ),
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Subsignal( "ba", Pins( "M18 H18 L17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "ras_n", Pins( "R17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "cas_n", Pins( "R16" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "we_n", Pins( "M17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "cs_n", Pins( "P17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "dm", Pins( "F20 T18" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "dq", Pins( "J20 F19 J19 E19 K19 E20 K20 G20 ",
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"T17 U16 P18 U17 N19 U18 P19 U19" ),
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IOStandard( "SSTL15_I" ), Misc( "TERMINATION=50" ) ),
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Subsignal( "dqs_p", Pins( "G19 T19" ), IOStandard( "SSTL15D_I" ),
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Misc( "TERMINATION=OFF" ), Misc( "DIFFRESISTOR=100" ) ),
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Subsignal( "clk_p", Pins( "K16" ), IOStandard( "SSTL15D_I" ) ),
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Subsignal( "cke", Pins( "D19" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "odt", Pins( "H4" ) ), # FIXME not connected
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Subsignal( "reset_n", Pins( "L20" ), IOStandard( "SSTL15_I" ) ),
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# Pseudo-VCCIO pads: SSTL15_II for 10 mA drive strength, see
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# FPGA-TN-02035, section 6.7.
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Subsignal( "vccio", Pins( "C20 E16 J18 K18 L18 L19 N17 N18 T16" ),
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IOStandard( "SSTL15_II" ) ),
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Misc( "SLEWRATE=FAST" ) ),
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# MII Ethernet
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("eth_clocks", 0,
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Subsignal("rx", Pins("L5")),
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Subsignal("tx", Pins("P1")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rx_data", Pins("N3 N4 N5 P4")),
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Subsignal("rx_dv", Pins("M5")),
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Subsignal("tx_data", Pins("N1 L4 L3 K4")),
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Subsignal("tx_en", Pins("P2")),
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Subsignal("mdc", Pins("P5")),
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Subsignal("mdio", Pins("J5")),
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Subsignal("rx_er", Pins("K5")),
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Subsignal("int_n", Pins("M4")),
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Subsignal("rst_n", Pins("C9")), # FIXME not connected
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IOStandard("LVCMOS33")
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),
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# HDMI output
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("hdmi", 0,
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Subsignal( "data0", Pins( "G3" ) ),
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Subsignal( "data1", Pins( "F4" ) ),
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Subsignal( "data2", Pins( "C1" ) ),
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Subsignal( "clk", Pins( "E4" ) ),
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IOStandard( "LVCMOS33D" ), Misc( "DRIVE=8 SLEWRATE=FAST" ) ),
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# USB host 1
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("usbhost", 0,
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Subsignal( "dp", Pins( "B6" ) ),
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Subsignal( "dn", Pins( "A6" ) ),
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IOStandard( "LVCMOS33" ) )
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="trellis", **kwargs):
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LatticePlatform.__init__(self, "LFE5U-85F-8BG381", _io, _connectors, toolchain=toolchain, **kwargs)
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def request(self, *args, **kwargs):
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return LatticePlatform.request(self, *args, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_fpc_iii.cfg")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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@ -0,0 +1,17 @@
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adapter driver ftdi
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transport select jtag
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# ftdi_device_desc "FPC-III" (once programmed)
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ftdi_vid_pid 0x1209 0xFC30 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0xfff8 0xfffb
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ftdi_layout_signal LED -ndata 0x10
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reset_config none
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# default speed
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adapter speed 25000
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# ECP5 device - LFE5U-85
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x41113043
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@ -0,0 +1,180 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import fpc_iii
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import IS43TR16256A
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk25 = platform.request("clk25")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk25)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout,
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),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, **kwargs):
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platform = fpc_iii.Platform(toolchain=toolchain)
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if kwargs[ "uart_name" ] == "serial":
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kwargs[ "uart_name" ] = "usb_fifo"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on FPC-III",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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ddram = platform.request("ddram")
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# Pin K16 (PR29A) is available as the true component of a
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# differential pair, and K17 (PR29B) is its complement.
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# So the clk_polarity=1 parameter would be necessary only if
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# some idiot were laying out the board and wired K16 to
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# the DDR3 CK-, and K17 to CK+. The chances of that
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# happening are remote, of course.
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self.submodules.ddrphy = ECP5DDRPHY( ddram, sys_clk_freq, clk_polarity=1 )
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self.ddrphy.settings.rtt_nom = "disabled"
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.comb += ddram.vccio.eq( Replicate( C(1), ddram.vccio.nbits ) )
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = IS43TR16256A(sys_clk_freq, "1:2"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x20000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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self.comb += platform.request("dram_vtt_en").eq( 0 if self.integrated_main_ram_size else 1 )
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_csr("ethphy")
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on FPC-III")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
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parser.add_argument("--sys-clk-freq", default=80e6, help="system clock frequency (default=80MHz)")
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parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
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parser.add_argument("--with-etherbone", action="store_true", help="enable Ethernet wishbone support")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support")
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builder_args(parser)
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soc_sdram_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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assert not (args.with_ethernet and args.with_etherbone)
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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**soc_sdram_argdict(args))
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assert not (args.with_spi_sdcard and args.with_sdcard)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
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if __name__ == "__main__":
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main()
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