enjoy-digital
GitHub
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# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk50", 0, Pins("V11"), IOStandard("3.3-V LVTTL")),
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("clk50", 1, Pins("Y13"), IOStandard("3.3-V LVTTL")),
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("clk50", 2, Pins("E11"), IOStandard("3.3-V LVTTL")),
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("user_led", 0, Pins("W15"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("AA24"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("V16"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("V15"), IOStandard("3.3-V LVTTL")),
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("user_led", 4, Pins("AF26"), IOStandard("3.3-V LVTTL")),
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("user_led", 5, Pins("AE26"), IOStandard("3.3-V LVTTL")),
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("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")),
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("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")),
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("user_sw", 0, Pins("Y24"), IOStandard("3.3-V LVTTL")),
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("user_sw", 1, Pins("W24"), IOStandard("3.3-V LVTTL")),
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("user_sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")),
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("user_sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1
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Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
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),
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("g_sensor", 0,
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Subsignal("int", Pins("A17")),
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Subsignal("sclk", Pins("C18")),
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Subsignal("sdat", Pins("A19")),
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IOStandard("3.3-V LVTTL")
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),
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("adc", 0,
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Subsignal("convst", Pins("U9")),
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Subsignal("sclk", Pins("V10")),
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Subsignal("sdi", Pins("AC4")),
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Subsignal("sdo", Pins("AD4")),
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IOStandard("3.3-V LVTTL")
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),
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("hdmi", 0,
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Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
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Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),
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Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")),
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Subsignal("tx_clk", Pins("AG5")),
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Subsignal("tx_de", Pins("AD19")),
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Subsignal("tx_hs", Pins("T8")),
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Subsignal("tx_vs", Pins("V13")),
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Subsignal("tx_int", Pins("AF11")),
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Subsignal("i2s0", Pins("T13")),
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Subsignal("mclk", Pins("U11")),
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Subsignal("lrclk", Pins("T11")),
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Subsignal("sclk", Pins("T12")),
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Subsignal("scl", Pins("U10")),
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Subsignal("sda", Pins("AA4")),
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IOStandard("3.3-V LVTTL")
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),
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("gpio_0", 0,
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Pins("V12 E8 W12 D11 D8 AH13 AF7 AH14 AF4 AH3 AD5 AG14 AE23 D12 AD20",
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"C12 AD17 AC23 AC22 Y19 AB23 AA19 W11 AA18 W14 Y18 Y17 AB25 AB26",
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"Y11 AA26 AA13 AA11"),
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IOStandard("3.3-V LVTTL")
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),
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("gpio_1", 0,
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Pins("Y15 AC24 AA15 AD26 AG28 AF28 AE25 AF27 AG26 AH27 AG25 AH26 AH24",
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"AF25 AG23 AF24 AG24 AH22 AH21 AG21 AH23 AA20 AF22 AE22 AG20 AF21",
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"AH23 AA20 AF22 AE22 AG20 AF21 AG19 AH19 AG18 AH18 AF18 AF20 AG15",
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"AE20 AE19 AE17"),
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IOStandard("3.3-V LVTTL")
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),
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("arduino", 0,
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Pins("AG13 AF13 AG10 AG9 U14 U13 AG8 AH8 AF17 AE15 AF15 AG16 AH11 AH12",
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"AH9, AG11, AH7"),
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IOStandard("3.3-V LVTTL")
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),
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]
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_mister_sdram_module_io = [
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("sdram_clock", 0, Pins("AD20"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("cke", Pins("AG10")),
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Subsignal("a", Pins(
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"Y11 AA26 AA13 AA11 W11 Y19 AB23 AC23 AC22 C12 AB26 AD17 D12")),
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Subsignal("dq", Pins(
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"E8 V12 D11 W12 AH13 D8 AH14 AF7 AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3")),
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Subsignal("ba", Pins(
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"Y17 AB25")),
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Subsignal("cas_n", Pins("AA18")),
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Subsignal("cs_n", Pins("Y18")),
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Subsignal("ras_n", Pins("W14")),
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Subsignal("we_n", Pins("AA19")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self):
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AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io)
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self.add_extension(_mister_sdram_module_io)
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def create_programmer(self):
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return USBBlaster()
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@ -0,0 +1,125 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import de10nano
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import AS4C16M16
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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platform.add_period_constraint(clk50, 1e9/50e6)
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# PLL
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pll_locked = Signal()
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pll_clk_out = Signal(6)
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self.specials += \
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Instance("ALTPLL",
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p_BANDWIDTH_TYPE = "AUTO",
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p_CLK0_DIVIDE_BY = 1,
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p_CLK0_DUTY_CYCLE = 50,
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p_CLK0_MULTIPLY_BY = 1,
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p_CLK0_PHASE_SHIFT = "0",
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p_CLK1_DIVIDE_BY = 1,
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p_CLK1_DUTY_CYCLE = 50,
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p_CLK1_MULTIPLY_BY = 1,
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p_CLK1_PHASE_SHIFT = "-10000",
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p_COMPENSATE_CLOCK = "CLK0",
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p_INCLK0_INPUT_FREQUENCY = 20000,
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p_OPERATION_MODE = "NORMAL",
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i_INCLK = clk50,
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o_CLK = pll_clk_out,
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i_ARESET = 0,
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i_CLKENA = 0x3f,
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i_EXTCLKENA = 0xf,
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i_FBIN = 1,
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i_PFDENA = 1,
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i_PLLENA = 1,
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o_LOCKED = pll_locked,
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)
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self.comb += [
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self.cd_sys.clk.eq(pll_clk_out[0]),
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self.cd_sys_ps.clk.eq(pll_clk_out[1]),
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]
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
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AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
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]
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = de10nano.Platform()
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# SoCCore ---------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform)
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# SDRAMSoC ------------------------------------------------------------------------------------------
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class SDRAMSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = de10nano.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform)
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# SDR SDRAM --------------------------------------------------------------------------------
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = AS4C16M16(self.clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano")
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parser.add_argument("--with-sdram", action="store_true",
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help="enable MiSTer SDRAM expansion board")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = None
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if args.with_sdram:
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soc = SDRAMSoC(**soc_sdram_argdict(args))
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else:
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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