Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

colorlight_5a_75b: set RGMII tx/rx_delay to 0ns in the FPGA (added by PCB/PHY)

Browse source
This commit is contained in:
Florent Kermarrec 2020-01-23 09:39:48 +01:00
parent dcc65b347d
commit 4fb89fc9c5
1 changed files with 3 additions and 1 deletions

4
litex_boards/partner/targets/colorlight_5a_75b.py
View file

@ -67,7 +67,9 @@ class EtherboneSoC(BaseSoC):
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy))
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9, # No FPGA delay (Clk/Data delay added by PCB/PHY)
rx_delay = 0e-9) # No FPGA delay (Clk/Data delay added by PCB/PHY)
self.add_csr("ethphy")
# core
self.submodules.ethcore = LiteEthUDPIPCore(