targets: Replace self.add_wb_master with self.bus.add_master.

litex_boards/targets/alinx_axu2cga.py

@@ -91,7 +91,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(2, 32),
                 wishbone     = wb_lpd,
                 base_address = self.mem_map['csr'])
-            self.add_wb_master(wb_lpd)
+            self.bus.add_master(master=wb_lpd)
 
             self.bus.add_region("sram", SoCRegion(
                 origin = self.cpu.mem_map["sram"],

litex_boards/targets/digilent_arty_z7.py

@@ -83,7 +83,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = self.mem_map['csr'])
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

litex_boards/targets/digilent_pynq_z1.py

@@ -81,7 +81,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = 0x43c00000)
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:

litex_boards/targets/digilent_zedboard.py

@@ -75,7 +75,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = self.mem_map["csr"])
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
 
             self.bus.add_region("sram", SoCRegion(
                 origin=self.cpu.mem_map["sram"],

litex_boards/targets/krtkl_snickerdoodle.py

@@ -93,7 +93,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = self.mem_map['csr'])
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

litex_boards/targets/redpitaya.py

@@ -73,7 +73,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = 0x43c00000)
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

litex_boards/targets/siglent_sds1104xe.py

@@ -129,7 +129,7 @@ class BaseSoC(SoCCore):
 
             # Etherbone
             self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
-            self.add_wb_master(self.etherbone.wishbone.bus)
+            self.bus.add_master(master=self.etherbone.wishbone.bus)
 
             # Timing constraints
             eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk

litex_boards/targets/sqrl_fk33.py

@@ -105,7 +105,7 @@ class BaseSoC(SoCCore):
             # Wishbone bridge
             self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
                 base_address = self.mem_map["csr"])
-            self.add_wb_master(self.pcie_bridge.wishbone)
+            self.bus.add_master(master=self.pcie_bridge.wishbone)
 
             # DMA0
             self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,

litex_boards/targets/xilinx_kv260.py

@@ -132,7 +132,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = self.mem_map["csr"])
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
             self.bus.add_region("sram", SoCRegion(
                 origin=self.cpu.mem_map["sram"],
                 size=2 * 1024 * 1024 * 1024)  # DDR

litex_boards/targets/xilinx_zcu216.py

@@ -112,7 +112,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = self.mem_map["csr"])
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
             self.bus.add_region("sram", SoCRegion(
                 origin = self.cpu.mem_map["sram"],
                 size   = 2 * 1024 * 1024 * 1024)  # DDR

litex_boards/targets/xilinx_zybo_z7.py

@@ -67,7 +67,7 @@ class BaseSoC(SoCCore):
                 axi          = self.cpu.add_axi_gp_master(),
                 wishbone     = wb_gp0,
                 base_address = 0x43c00000)
-            self.add_wb_master(wb_gp0)
+            self.bus.add_master(master=wb_gp0)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser: