partner/aller,nereid & tagus: fix compilation
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@ -50,7 +50,7 @@ class CRG(Module):
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# AllerSoC -----------------------------------------------------------------------------------------
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# AllerSoC -----------------------------------------------------------------------------------------
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class AllerSoC(SoCSDRAM):
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class AllerSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x00000000
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SoCSDRAM.mem_map["csr"] = 0x80000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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def __init__(self, platform, with_pcie_uart=True):
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def __init__(self, platform, with_pcie_uart=True):
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@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM):
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# pcie wishbone bridge
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.shadow_base)
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lambda a: 1, shadow_base=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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# pcie dma
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@ -50,7 +50,7 @@ class CRG(Module):
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# NereidSoC ----------------------------------------------------------------------------------------
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# NereidSoC ----------------------------------------------------------------------------------------
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class NereidSoC(SoCSDRAM):
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class NereidSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x00000000
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SoCSDRAM.mem_map["csr"] = 0x80000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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def __init__(self, platform, with_pcie_uart=True):
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def __init__(self, platform, with_pcie_uart=True):
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@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM):
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# pcie wishbone bridge
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.shadow_base)
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lambda a: 1, shadow_base=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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# pcie dma
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@ -52,7 +52,7 @@ class CRG(Module):
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# TagusSoC -----------------------------------------------------------------------------------------
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# TagusSoC -----------------------------------------------------------------------------------------
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class TagusSoC(SoCSDRAM):
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class TagusSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x00000000
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SoCSDRAM.mem_map["csr"] = 0x80000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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def __init__(self, platform, with_pcie_uart=True):
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def __init__(self, platform, with_pcie_uart=True):
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@ -97,9 +97,7 @@ class TagusSoC(SoCSDRAM):
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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self.pcie_phy.cd_pcie.clk.attr.add("keep")
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self.pcie_phy.cd_pcie.clk.attr.add("keep")
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platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
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platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.crg.cd_sys.clk,
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self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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self.add_csr("pcie_phy")
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# pcie endpoint
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# pcie endpoint
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@ -107,7 +105,7 @@ class TagusSoC(SoCSDRAM):
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# pcie wishbone bridge
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.shadow_base)
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lambda a: 1, shadow_base=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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# pcie dma
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