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partner/aller,nereid & tagus: fix compilation

This commit is contained in:
Florent Kermarrec 2019-12-03 09:37:18 +01:00
parent f7fbfb4639
commit 5193f7155a
3 changed files with 8 additions and 10 deletions
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6
litex_boards/partner/targets/aller.py
View File

@ -50,7 +50,7 @@ class CRG(Module):
# AllerSoC ----------------------------------------------------------------------------------------- # AllerSoC -----------------------------------------------------------------------------------------
class AllerSoC(SoCSDRAM): class AllerSoC(SoCSDRAM):
SoCSDRAM.mem_map["csr"] = 0x00000000 SoCSDRAM.mem_map["csr"] = 0x80000000
SoCSDRAM.mem_map["rom"] = 0x20000000 SoCSDRAM.mem_map["rom"] = 0x20000000
def __init__(self, platform, with_pcie_uart=True): def __init__(self, platform, with_pcie_uart=True):
@ -88,7 +88,7 @@ class AllerSoC(SoCSDRAM):
sdram_module = MT41J128M16(sys_clk_freq, "1:4") sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings) timing_settings = sdram_module.timing_settings)
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
# pcie phy # pcie phy
@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.shadow_base) lambda a: 1, shadow_base=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma

4
litex_boards/partner/targets/nereid.py
View File

@ -50,7 +50,7 @@ class CRG(Module):
# NereidSoC ---------------------------------------------------------------------------------------- # NereidSoC ----------------------------------------------------------------------------------------
class NereidSoC(SoCSDRAM): class NereidSoC(SoCSDRAM):
SoCSDRAM.mem_map["csr"] = 0x00000000 SoCSDRAM.mem_map["csr"] = 0x80000000
SoCSDRAM.mem_map["rom"] = 0x20000000 SoCSDRAM.mem_map["rom"] = 0x20000000
def __init__(self, platform, with_pcie_uart=True): def __init__(self, platform, with_pcie_uart=True):
@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.shadow_base) lambda a: 1, shadow_base=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma

8
litex_boards/partner/targets/tagus.py
View File

@ -52,7 +52,7 @@ class CRG(Module):
# TagusSoC ----------------------------------------------------------------------------------------- # TagusSoC -----------------------------------------------------------------------------------------
class TagusSoC(SoCSDRAM): class TagusSoC(SoCSDRAM):
SoCSDRAM.mem_map["csr"] = 0x00000000 SoCSDRAM.mem_map["csr"] = 0x80000000
SoCSDRAM.mem_map["rom"] = 0x20000000 SoCSDRAM.mem_map["rom"] = 0x20000000
def __init__(self, platform, with_pcie_uart=True): def __init__(self, platform, with_pcie_uart=True):
@ -97,9 +97,7 @@ class TagusSoC(SoCSDRAM):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep") self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints( platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")
# pcie endpoint # pcie endpoint
@ -107,7 +105,7 @@ class TagusSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.shadow_base) lambda a: 1, shadow_base=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma