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platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.

This commit is contained in:
Florent Kermarrec 2021-03-03 18:05:24 +01:00
parent 465a95d2a6
commit 51a0bbfa65
6 changed files with 50 additions and 79 deletions
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12
litex_boards/platforms/de10nano.py
View File

@ -150,12 +150,12 @@ _mister_sdram_module_io = [
# VGA
("vga", 0,
Subsignal("red", Pins("AE17 AE20 AF20 AH18 AH19 AF21")),
Subsignal("green", Pins("AE19 AG15 AF18 AG18 AG19 AG20")),
Subsignal("blue", Pins("AG21 AA20 AE22 AF22 AH23 AH21")),
Subsignal("hsync", Pins("AH22")),
Subsignal("vsync", Pins("AG24")),
Subsignal("en", Pins("AH27")),
Subsignal("en", Pins("AH27")),
Subsignal("hsync_n", Pins("AH22")),
Subsignal("vsync_n", Pins("AG24")),
Subsignal("r", Pins("AE17 AE20 AF20 AH18 AH19 AF21")),
Subsignal("g", Pins("AE19 AG15 AF18 AG18 AG19 AG20")),
Subsignal("b", Pins("AG21 AA20 AE22 AF22 AH23 AH21")),
IOStandard("3.3-V LVTTL")
),
]

4
litex_boards/platforms/mist.py
View File

@ -27,11 +27,11 @@ _io = [
# VGA
("vga", 0,
Subsignal("hsync_n", Pins("119")),
Subsignal("vsync_n", Pins("136")),
Subsignal("r", Pins("135 137 141 142 143 144")),
Subsignal("g", Pins("106 110 111 112 113 114")),
Subsignal("b", Pins("115 120 121 125 132 133")),
Subsignal("vsync", Pins("136")),
Subsignal("hsync", Pins("119")),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
),

35
litex_boards/targets/de10lite.py
View File

@ -21,13 +21,12 @@ from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
@ -48,7 +47,7 @@ class _CRG(Module):
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_vga, 25e6)
pll.create_clkout(self.cd_vga, 40e6)
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
@ -56,7 +55,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
platform = de10lite.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -81,18 +80,10 @@ class BaseSoC(SoCCore):
l2_cache_reverse = True
)
# VGA Terminal -----------------------------------------------------------------------------
if with_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync_n.eq(terminal.vsync),
vga_pads.hsync_n.eq(terminal.hsync),
vga_pads.r.eq(terminal.red[4:8]),
vga_pads.g.eq(terminal.green[4:8]),
vga_pads.b.eq(terminal.blue[4:8])
]
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
@ -104,17 +95,17 @@ class BaseSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_vga = args.with_vga,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))

43
litex_boards/targets/de10nano.py
View File

@ -21,13 +21,12 @@ from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser
from litedram.modules import AS4C32M16
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
@ -56,7 +55,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_vga, 25e6)
pll.create_clkout(self.cd_vga, 40e6)
# SDRAM clock
if with_sdram:
@ -66,7 +65,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=True, with_mister_vga=False, sdram_rate="1:1", **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=True, with_mister_video_terminal=False, sdram_rate="1:1", **kwargs):
platform = de10nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -92,18 +91,10 @@ class BaseSoC(SoCCore):
l2_cache_reverse = True
)
# VGA terminal -----------------------------------------------------------------------------
if with_mister_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[2:8]),
vga_pads.green.eq(terminal.green[2:8]),
vga_pads.blue.eq(terminal.blue[2:8])
]
# Video Terminal ---------------------------------------------------------------------------
if with_mister_video_terminal:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
@ -115,21 +106,21 @@ class BaseSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
parser.add_argument("--with-mister-video-terminal", action="store_true", help="Enable Video Terminal with Mister expansion board")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_mister_sdram = args.with_mister_sdram,
with_mister_vga = args.with_mister_vga,
sdram_rate = args.sdram_rate,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_mister_sdram = args.with_mister_sdram,
with_mister_video_terminal = args.with_mister_video_terminal,
sdram_rate = args.sdram_rate,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))

2
litex_boards/targets/deca.py
View File

@ -23,8 +23,6 @@ from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):

33
litex_boards/targets/mist.py
View File

@ -21,13 +21,12 @@ from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser
from litedram.modules import MT48LC16M16
from litedram.phy import GENSDRPHY
from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
@ -48,7 +47,7 @@ class _CRG(Module):
pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_vga, 25e6)
pll.create_clkout(self.cd_vga, 40e6)
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
@ -56,7 +55,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
platform = mist.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -81,18 +80,10 @@ class BaseSoC(SoCCore):
l2_cache_reverse = True
)
# VGA Terminal -----------------------------------------------------------------------------
if with_vga:
self.submodules.terminal = terminal = Terminal()
self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
vga_pads = platform.request("vga")
self.comb += [
vga_pads.vsync.eq(terminal.vsync),
vga_pads.hsync.eq(terminal.hsync),
vga_pads.r.eq(terminal.red[2:8]),
vga_pads.g.eq(terminal.green[2:8]),
vga_pads.b.eq(terminal.blue[2:8])
]
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
@ -104,17 +95,17 @@ class BaseSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on MIST")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_vga=args.with_vga,
with_video_terminal=args.with_video_terminal,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))