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1bitsquared_icebreaker: Enable LiteSPI Master but reduce FIFO depth to reduce resource usage. 

Already better regarding resource usage:
Info: 	         ICESTORM_LC:  2938/ 5280    55%
Info: 	        ICESTORM_RAM:     2/   30     6%
Info: 	               SB_IO:    15/   96    15%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     0/    1     0%
Info: 	        ICESTORM_DSP:     0/    8     0%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     0/    2     0%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     0/    1     0%
Info: 	         SB_RGBA_DRV:     0/    1     0%
Info: 	      ICESTORM_SPRAM:     4/    4   100%
This commit is contained in:
Florent Kermarrec 2021-07-27 17:38:25 +02:00
parent 12fb315e09
commit 533d25e845
1 changed files with 1 additions and 1 deletions
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2
litex_boards/targets/1bitsquared_icebreaker.py
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@ -104,7 +104,7 @@ class BaseSoC(SoCCore):
from litespi.phy.generic import LiteSPIPHY
from litespi import LiteSPI
self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), W25Q128JV(Codes.READ_1_1_4))
self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, with_master=False, mmap_endianness=self.cpu.endianness)
self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, master_fifo_depth=1, mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=W25Q128JV.total_size, cached=False)
self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region)
else: