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antmicro_datacenter: use A7DDRPHY 

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala 2022-01-17 12:47:39 +01:00 committed by Alessandro Comodi
parent 73b5143cec
commit 5359fc5bfc
1 changed files with 12 additions and 10 deletions
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6
litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
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@ -21,7 +21,7 @@ from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litedram.modules import MTA18ASF2G72PZ from litedram.modules import MTA18ASF2G72PZ
from litedram.phy.s7ddrphy import K7DDRPHY from litedram.phy.s7ddrphy import A7DDRPHY
from liteeth.phy import LiteEthS7PHYRGMII from liteeth.phy import LiteEthS7PHYRGMII
from litex.soc.cores.hyperbus import HyperRAM from litex.soc.cores.hyperbus import HyperRAM
@ -33,6 +33,7 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_idelay = ClockDomain()
# # # # # #
@ -42,6 +43,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, iodelay_clk_freq) pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
@ -65,7 +67,7 @@ class BaseSoC(SoCCore):
# DDR4 SDRAM RDIMM ------------------------------------------------------------------------- # DDR4 SDRAM RDIMM -------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.ddrphy = K7DDRPHY(platform.request("ddr4"), self.submodules.ddrphy = A7DDRPHY(platform.request("ddr4"),
memtype = "DDR4", memtype = "DDR4",
iodelay_clk_freq = iodelay_clk_freq, iodelay_clk_freq = iodelay_clk_freq,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,