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arrow_sockit: review/harmonize with others boards.

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This commit is contained in:
Florent Kermarrec 2021-01-25 09:14:46 +01:00
parent 4adc1b14c4
commit 537f494cbb
2 changed files with 41 additions and 45 deletions
litex_boards
platforms
arrow_sockit.py
targets
arrow_sockit.py

36
litex_boards/platforms/arrow_sockit.py
View file

@ -1,9 +1,7 @@
# #
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
# I (HB) used the similar de1soc board as a starting point, therefore: # Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# SocKit adaption (c) 2020 Hans Baier <hansfbaier@gmail.com>
# #
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
@ -41,12 +39,11 @@ _io = [
"AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13", "AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13",
"AH13 AH14 AJ9 AK9 AK7 AK8 AG12"), "AH13 AH14 AJ9 AK9 AK7 AK8 AG12"),
IOStandard("SSTL15"), IOStandard("SSTL15"),
Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")
), ),
Subsignal("ba", Pins("AH10 AJ11 AK11"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("ba", Pins("AH10 AJ11 AK11"), IOStandard("SSTL-15 CLASS I"), ),
Subsignal("ras_n", Pins("AH8"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("ras_n", Pins("AH8"), IOStandard("SSTL-15 CLASS I")),
Subsignal("cas_n", Pins("AH7"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("cas_n", Pins("AH7"), IOStandard("SSTL-15 CLASS I")),
Subsignal("we_n", Pins("AJ6"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("we_n", Pins("AJ6"), IOStandard("SSTL-15 CLASS I")),
Subsignal("dm", Pins("AH17 AG23 AK23 AJ27"), Subsignal("dm", Pins("AH17 AG23 AK23 AJ27"),
IOStandard("SSTL-15 CLASS I"), IOStandard("SSTL-15 CLASS I"),
Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION") Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION")
@ -80,11 +77,12 @@ _io = [
Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"),
Misc("D5_DELAY=2") Misc("D5_DELAY=2")
), ),
Subsignal("cs_n", Pins("AB15"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("cs_n", Pins("AB15"), IOStandard("SSTL-15 CLASS I")),
Subsignal("cke", Pins("AJ21"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("cke", Pins("AJ21"), IOStandard("SSTL-15 CLASS I")),
Subsignal("odt", Pins("AE16"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("odt", Pins("AE16"), IOStandard("SSTL-15 CLASS I")),
Subsignal("reset_n", Pins("AK21"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), Subsignal("reset_n", Pins("AK21"), IOStandard("SSTL-15 CLASS I")),
Subsignal("rzq", Pins("AG1"), IOStandard("SSTL-15")), Subsignal("rzq", Pins("AG1"), IOStandard("SSTL-15")),
Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")
), ),
# VGA # VGA
@ -99,11 +97,13 @@ _io = [
IOStandard("3.3-V LVTTL") IOStandard("3.3-V LVTTL")
), ),
# IrDA
("irda", 0, ("irda", 0,
Subsignal("irda_rxd", Pins("AH2")), Subsignal("irda_rxd", Pins("AH2")),
IOStandard("3.3-V LVTTL") IOStandard("3.3-V LVTTL")
), ),
# Temperatue
("temperature", 0, ("temperature", 0,
Subsignal("temp_cs_n", Pins("AF8")), Subsignal("temp_cs_n", Pins("AF8")),
Subsignal("temp_din", Pins("AG7")), Subsignal("temp_din", Pins("AG7")),
@ -112,6 +112,7 @@ _io = [
IOStandard("3.3-V LVTTL") IOStandard("3.3-V LVTTL")
), ),
# Audio
("audio", 0, ("audio", 0,
Subsignal("aud_adclrck", Pins("AG30")), Subsignal("aud_adclrck", Pins("AG30")),
Subsignal("aud_adcdat", Pins("AC27")), Subsignal("aud_adcdat", Pins("AC27")),
@ -126,6 +127,8 @@ _io = [
) )
] ]
# Connectors ---------------------------------------------------------------------------------------
_connectors_hsmc_gpio_daughterboard = [ _connectors_hsmc_gpio_daughterboard = [
("J2", "G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " + ("J2", "G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " +
"C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " + "C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " +
@ -146,19 +149,18 @@ _connectors_hsmc_gpio_daughterboard = [
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------
_device_map = { _device_map = {
"revB/C": "5CSXFC6D6F31C8ES", "revb" : "5CSXFC6D6F31C8ES",
"revD": "5CSXFC6D6F31C8", "revc" : "5CSXFC6D6F31C8ES",
"revd" : "5CSXFC6D6F31C8",
} }
class Platform(AlteraPlatform): class Platform(AlteraPlatform):
default_clk_name = "clk50" default_clk_name = "clk50"
default_clk_period = 1e9/50e6 default_clk_period = 1e9/50e6
def __init__(self, revision="revB/C"): def __init__(self, revision="revd"):
assert revision in _device_map.keys() assert revision in _device_map.keys()
self.revision = revision self.revision = revision
# Yes, the HSMC GPIO board is optional, but only it has generic connectors
AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard) AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard)
def create_programmer(self): def create_programmer(self):

16
litex_boards/targets/arrow_sockit.py
View file

@ -2,10 +2,7 @@
# #
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
# I (HB) used the similar de1soc board as a starting point, therefore: # Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# SocKit adaption (c) 2020 Hans Baier <hansfbaier@gmail.com>
#
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -15,7 +12,6 @@ from migen.fhdl.module import Module
from migen.fhdl.structure import Signal, ClockDomain from migen.fhdl.structure import Signal, ClockDomain
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import DDROutput
from litex.soc.cores.clock import CycloneVPLL from litex.soc.cores.clock import CycloneVPLL
from litex.soc.integration.builder import Builder, builder_args, builder_argdict from litex.soc.integration.builder import Builder, builder_args, builder_argdict
from litex.soc.integration.soc_core import SoCCore from litex.soc.integration.soc_core import SoCCore
@ -45,12 +41,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), revisionD=False, **kwargs): def __init__(self, sys_clk_freq=int(50e6), revision="revd", **kwargs):
revision = "revD" if revisionD else "revB/C"
platform = arrow_sockit.Platform(revision) platform = arrow_sockit.Platform(revision)
# Defaults to Crossover UART, because Serial is attached to the HPS # Defaults to Crossover UART because serial is attached to the HPS and cannot be used.
# and thus not available to the FPGA
if kwargs["uart_name"] == "serial": if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "crossover" kwargs["uart_name"] = "crossover"
@ -76,7 +70,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit") parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revisionD", action="store_true", help="board revision D, otherwise the more widespread revision B/C is assumed") parser.add_argument("--revision", default="revd", help="Board revision: revb (default), revc or revd")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
@ -84,7 +78,7 @@ def main():
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
revisionD = args.revisionD, revision = args.revision,
**soc_sdram_argdict(args) **soc_sdram_argdict(args)
) )
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))