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decklink_quad_hdmi_recorder: Add INTERNAL_VREF constraint on DRAM banks.

This commit is contained in:
Florent Kermarrec 2021-07-02 14:32:14 +02:00
parent 7442639a5e
commit 548f77c79c
1 changed files with 3 additions and 0 deletions
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3
litex_boards/platforms/decklink_quad_hdmi_recorder.py
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@ -172,3 +172,6 @@ class Platform(XilinxPlatform):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6) self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_platform_command("set_property INTERNAL_VREF 0.75 [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF 0.75 [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF 0.75 [get_iobanks 46]")