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litex-boards
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target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX).

This commit is contained in:
Florent Kermarrec 2020-11-27 18:53:45 +01:00
parent 20903da54a
commit 5a4e28d47d
3 changed files with 3 additions and 4 deletions
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2
litex_boards/targets/fomu.py
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@ -84,7 +84,7 @@ class BaseSoC(SoCCore):
# Serial -----------------------------------------------------------------------------------
# FIXME: do proper install of ValentyUSB.
# FIXME: replace IoBuf with https://github.com/im-tomu/valentyusb/blob/master/valentyusb/usbcore/io.py#L13-L61.
os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri")
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------

3
litex_boards/targets/logicbone.py
View File

@ -9,7 +9,6 @@
import os
import sys
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
@ -103,7 +102,7 @@ class BaseSoC(SoCCore):
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "usb_acm":
# FIXME: do proper install of ValentyUSB.
os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri")
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------

2
litex_boards/targets/orangecrab.py
View File

@ -151,7 +151,7 @@ class BaseSoC(SoCCore):
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "usb_acm":
# FIXME: do proper install of ValentyUSB.
os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri")
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
else:
platform.add_extension(orangecrab.feather_serial)