initiate target and platform for alveo_u280 board
This commit is contained in:
Sergiu Mosanu
parent
6a5f2f59a6
commit
5a73eb0b6d
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 David Shah <dave@ds0.me>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("sysclk", 0,
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Subsignal("n", Pins("BJ44"), IOStandard("LVDS")),
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Subsignal("p", Pins("BJ43"), IOStandard("LVDS")),
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),
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("sysclk", 1,
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Subsignal("n", Pins("BJ6"), IOStandard("LVDS")),
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Subsignal("p", Pins("BH6"), IOStandard("LVDS")),
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),
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("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")),
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# Leds
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("user_led", 0, Pins("C32"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("D32"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("D31"), IOStandard("LVCMOS18")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("A28"), IOStandard("LVCMOS18")),
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Subsignal("tx", Pins("B33"), IOStandard("LVCMOS18")),
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),
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# # PCIe
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# ("pcie_x2", 0,
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# Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
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# Subsignal("clk_n", Pins("AM10")),
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# Subsignal("clk_p", Pins("AM11")),
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# Subsignal("rx_n", Pins("AF1 AG3")),
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# Subsignal("rx_p", Pins("AF2 AG4")),
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# Subsignal("tx_n", Pins("AF6 AG8")),
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# Subsignal("tx_p", Pins("AF7 AG9")),
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# ),
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# ("pcie_x4", 0,
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# Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
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# Subsignal("clk_n", Pins("AM10")),
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# Subsignal("clk_p", Pins("AM11")),
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# Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3")),
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# Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4")),
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# Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8")),
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# Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")),
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# ),
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# ("pcie_x8", 0,
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# Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
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# Subsignal("clk_n", Pins("AM10")),
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# Subsignal("clk_p", Pins("AM11")),
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# Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3")),
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# Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4 AK2 AL4 AM2 AN4")),
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# Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8 AK6 AL8 AM6 AN8")),
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# Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9")),
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# ),
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# ("pcie_x16", 0,
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# Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
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# Subsignal("clk_n", Pins("AM10")),
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# Subsignal("clk_p", Pins("AM11")),
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# Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3 AP1 AR3 AT1 AU3 AV1 AW3 BA1 BC1")),
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# Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4 AK2 AL4 AM2 AN4 AP2 AR4 AT2 AU4 AV2 AW4 BA2 BC2")),
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# Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8 AK6 AL8 AM6 AN8 AP6 AR8 AT6 AU8 AV6 BB4 BD4 BF4")),
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# Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9 AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")),
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# ),
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# DDR4 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"BF46 BG43 BK45 BF42 BL45 BF43 BG42 BL43",
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"BK43 BM42 BG45 BD41 BL42 BE44"), #"BE43 BL46 BH44"
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IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("BH41"), IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")),
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Subsignal("clk_n", Pins("BJ46"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_p", Pins("BH46"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
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Subsignal("dq", Pins(
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"BN32 BP32 BL30 BM30 BP29 BP28 BP31 BN31",
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"BJ31 BH31 BF32 BF33 BH29 BH30 BF31 BG32",
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"BK31 BL31 BK33 BL33 BL32 BM33 BN34 BP34",
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"BH34 BH35 BF35 BF36 BJ33 BJ34 BG34 BG35",
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"BM52 BL53 BL52 BL51 BN50 BN51 BN49 BM48",
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"BE50 BE49 BE51 BD51 BF52 BF51 BG50 BF50",
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"BH50 BJ51 BH51 BH49 BK50 BK51 BJ49 BJ48",
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"BN44 BN45 BM44 BM45 BP43 BP44 BN47 BP47"),
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IOStandard("POD12_DCI"),
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# Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins(
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"BN30 BM29 BK30 BG30 BM35 BN35 BK35 BJ32",
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"BM50 BP49 BF48 BG49 BJ47 BK49 BP46 BP42"), #"BJ54 BJ53"
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IOStandard("DIFF_POD12"),
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# Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins(
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"BN29 BM28 BJ29 BG29 BL35 BM34 BK34 BH32",
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"BM49 BP48 BF47 BG48 BH47 BK48 BN46 BN42"), #"BH54 BJ52"
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IOStandard("DIFF_POD12"),
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# Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("BG33"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "sysclk"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("sysclk", 0, loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("sysclk", 1, loose=True), 1e9/100e6)
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# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
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# Reduce programming time
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self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
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# Other suggested configurations
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self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]")
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self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]")
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# ------------------------------------------------------------------------
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# # DDR4 memory channel C0 Clock constraint / Internal Vref
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# self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6)
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 40]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 41]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 42]")
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# # DDR4 memory channel C1 Clock constraint / Internal Vref
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# self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6)
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 67]")
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# # DDR4 memory channel C2 Clock constraint / Internal Vref
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# self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6)
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 47]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 48]")
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# # DDR4 memory channel C3 Clock constraint / Internal Vref
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# self.add_period_constraint(self.lookup_request("clk300", 3, loose=True), 1e9/300e6)
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]")
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# self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]")
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@ -0,0 +1,145 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import alveo_u280
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy import usddrphy
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, ddram_channel):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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#pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
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pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
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]
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self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs):
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platform = alveo_u280.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on AlveoU280",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(
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pads = platform.request("ddram", ddram_channel),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 500e6,
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is_rdimm = True)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")
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# Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
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self.add_ram("firmware_ram", 0x20000000, 0x8000)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_csr("pcie_phy")
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on AlveoU280")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
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parser.add_argument("--ddram-channel", default="0", help="DDRAM channel (default: 0)")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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ddram_channel = int(args.ddram_channel, 0),
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with_pcie = args.with_pcie,
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**soc_sdram_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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