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targets: Remove add_csr calls (no longer required).

This commit is contained in:
Florent Kermarrec 2022-10-21 08:42:24 +02:00
parent 377cda05a3
commit 5a8d846a86
5 changed files with 0 additions and 6 deletions
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2
litex_boards/targets/antmicro_artix_dc_scm.py
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@ -101,14 +101,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 128, data_width = 128,
bar0_size = 0x20000) bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1) self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/digilent_atlys.py
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@ -199,7 +199,6 @@ NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/ego1.py
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@ -54,7 +54,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/mnt_rkx7.py
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@ -123,7 +123,6 @@ class BaseSoC(SoCCore):
gpio_signals = platform.request("gpio") gpio_signals = platform.request("gpio")
self.submodules.leds = GPIOOut(gpio_signals) self.submodules.leds = GPIOOut(gpio_signals)
self.add_csr("leds")
# Additional I2C Ports --------------------------------------------------------------------- # Additional I2C Ports ---------------------------------------------------------------------
self.submodules.i2c0 = I2CMaster(platform.request("i2c", 0)) self.submodules.i2c0 = I2CMaster(platform.request("i2c", 0))

1
litex_boards/targets/trenz_te0725.py
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@ -54,7 +54,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------