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icebreaker/fomu: Split PSRAM in half: 64kB SRAM/64kB RAM).

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Allows building bare metal demo and running it directly on these boards.
This commit is contained in:
Florent Kermarrec 2021-09-29 19:33:22 +02:00
parent dfa572083a
commit 5addd7f7d8
3 changed files with 24 additions and 6 deletions
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10
litex_boards/targets/1bitsquared_icebreaker.py
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@ -90,9 +90,15 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
if not self.integrated_main_ram_size:
self.bus.add_region("main_ram", SoCRegion(
origin = self.bus.regions["sram"].origin + 64*kB,
size = 64*kB,
linker = True)
)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q128JV

10
litex_boards/targets/1bitsquared_icebreaker_bitsy.py
View file

@ -85,9 +85,15 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
if not self.integrated_main_ram_size:
self.bus.add_region("main_ram", SoCRegion(
origin = self.bus.regions["sram"].origin + 64*kB,
size = 64*kB,
linker = True)
)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q128JV

10
litex_boards/targets/kosagi_fomu.py
View file

@ -95,9 +95,15 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
if not self.integrated_main_ram_size:
self.bus.add_region("main_ram", SoCRegion(
origin = self.bus.regions["sram"].origin + 64*kB,
size = 64*kB,
linker = True)
)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV