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Merge pull request #16 from rohitk-singh/master 

partner: add platforms and targets for aller, tagus and nereid boards
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enjoy-digital 2019-09-02 11:31:46 +02:00 committed by GitHub
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litex_boards/partner/platforms/__init__.py
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from litex_boards.partner.platforms import aller
from litex_boards.partner.platforms import fomu_evt
from litex_boards.partner.platforms import fomu_hacker
from litex_boards.partner.platforms import fomu_pvt
from litex_boards.partner.platforms import nereid
from litex_boards.partner.platforms import netv2
from litex_boards.partner.platforms import tagus
from litex_boards.partner.platforms import tinyfpga_bx
from litex_boards.partner.platforms import trellisboard
from litex_boards.partner.platforms import ulx3s

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litex_boards/partner/platforms/aller.py Normal file
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clk / rst
("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")),
# leds (only a single rgb led, aliased here also)
("user_led", 0, Pins("AB21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AB22"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("U20"), IOStandard("LVCMOS33")),
# rgb led, active-low
("rgb_led", 0,
Subsignal("r", Pins("AB21")),
Subsignal("g", Pins("AB22")),
Subsignal("b", Pins("U20")),
IOStandard("LVCMOS33"),
),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("hold", Pins("R21")),
Subsignal("rst_n", Pins("R19")),
IOStandard("LVCMOS33")
),
("flash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("T19")),
Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
IOStandard("LVCMOS33")
),
# tpm
("tpm", 0,
Subsignal("clk", Pins("W20")),
Subsignal("rst_n", Pins("V19")),
Subsignal("cs_n", Pins("Y18")),
Subsignal("mosi", Pins("Y19")),
Subsignal("miso", Pins("V18")),
IOStandard("LVCMOS33"),
),
# pcie
("pcie", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8 D11 B10 D9")),
Subsignal("rx_n", Pins("A8 C11 A10 C9")),
Subsignal("tx_p", Pins("B4 D5 B6 D7")),
Subsignal("tx_n", Pins("A4 C5 A6 C7"))
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8")),
Subsignal("rx_n", Pins("A8")),
Subsignal("tx_p", Pins("B4")),
Subsignal("tx_n", Pins("A4"))
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 T5 Y6 T6 V2 T4 Y2 R2",
"Y1 R4 W5 W1 AA6 U2"
),
IOStandard("SSTL15")),
Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"
),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("U7"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]

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litex_boards/partner/platforms/nereid.py Normal file
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# rgb led, active-low
("rgb_led", 0,
Subsignal("r", Pins("J26")),
Subsignal("g", Pins("H26")),
Subsignal("b", Pins("G26")),
IOStandard("LVCMOS33"),
),
("clk100", 0, Pins("F22"), IOStandard("LVCMOS33")),
("clk150", 0,
Subsignal("p", Pins("G24"), IOStandard("TMDS_33")),
Subsignal("n", Pins("F24"), IOStandard("TMDS_33"))
),
# Active-high CPU reset, pulldown needed
("cpu_reset", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLDOWN=True")),
("fan_pwm", 0, Pins("J25"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("H22")),
Subsignal("rx", Pins("K22")),
Subsignal("rts", Pins("L22")),
Subsignal("cts", Pins("L23")),
Subsignal("cbus0", Pins("K23")),
IOStandard("LVCMOS33")
),
("xadc", 0,
Subsignal("adc_p", Pins("C16 A18 B17")),
Subsignal("adc_n", Pins("B16 A19 A17")),
Subsignal("v_p", Pins("N12")),
Subsignal("v_n", Pins("P11")),
),
("ddram", 0,
Subsignal("a", Pins(
"AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9",
"AD8 V9 Y11 Y7 W10 Y8 Y10 W9"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("AA8 AD9 AB9"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("AC13"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("AC12"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("AA13"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("AB12"), IOStandard("SSTL135")),
Subsignal("dm", Pins("W16 AD18 AE15 AB15 AD1 AC3 Y3 V6"),
IOStandard("SSTL135")),
Subsignal("dq", Pins(
"V19 V16 Y17 V14 V17 V18 W14 W15",
"AB17 AB19 AC18 AC19 AA19 AA20 AC17 AD19",
"AD16 AD15 AF20 AE17 AF17 AF19 AF14 AF15",
"AB16 AA15 AA14 AC14 AA18 AA17 AD14 AB14",
"AE3 AE6 AE2 AF3 AD4 AE5 AE1 AF2",
"AB6 Y6 AB4 AC4 AC6 AD6 Y5 AA4",
"AB2 AC2 V1 W1 V2 AA3 Y1 Y2",
"V4 V3 U2 U1 U7 W3 U6 U5"),
IOStandard("SSTL135_T_DCI")),
Subsignal("dqs_p", Pins("W18 AD20 AE18 Y15 AF5 AA5 AB1 W6"),
IOStandard("DIFF_SSTL135")),
Subsignal("dqs_n", Pins("W19 AE20 AF18 Y16 AF4 AB5 AC1 W5"),
IOStandard("DIFF_SSTL135")),
Subsignal("clk_p", Pins("V11"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("W11"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("AA10"), IOStandard("SSTL135")),
Subsignal("odt", Pins("AD13"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("AA2"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
("ddram_dual_rank", 0,
Subsignal("a", Pins(
"AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9",
"AD8 V9 Y11 Y7 W10 Y8 Y10 W9"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("AA8 AD9 AB9"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("AC13"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("AC12"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("AA13"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("AB12 AA12"), IOStandard("SSTL135")),
Subsignal("dm", Pins("W16 AD18 AE15 AB15 AD1 AC3 Y3 V6"),
IOStandard("SSTL135")),
Subsignal("dq", Pins(
"V19 V16 Y17 V14 V17 V18 W14 W15",
"AB17 AB19 AC18 AC19 AA19 AA20 AC17 AD19",
"AD16 AD15 AF20 AE17 AF17 AF19 AF14 AF15",
"AB16 AA15 AA14 AC14 AA18 AA17 AD14 AB14",
"AE3 AE6 AE2 AF3 AD4 AE5 AE1 AF2",
"AB6 Y6 AB4 AC4 AC6 AD6 Y5 AA4",
"AB2 AC2 V1 W1 V2 AA3 Y1 Y2",
"V4 V3 U2 U1 U7 W3 U6 U5"),
IOStandard("SSTL135_T_DCI")),
Subsignal("dqs_p", Pins("W18 AD20 AE18 Y15 AF5 AA5 AB1 W6"),
IOStandard("DIFF_SSTL135_T_DCI")),
Subsignal("dqs_n", Pins("W19 AE20 AF18 Y16 AF4 AB5 AC1 W5"),
IOStandard("DIFF_SSTL135_T_DCI")),
Subsignal("clk_p", Pins("V11 V8"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("W11 V7"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("AA10 AB10"), IOStandard("SSTL135")),
Subsignal("odt", Pins("AD13 Y13"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("AA2"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("C23")),
Subsignal("dq", Pins("B24", "A25", "B22", "A22")),
IOStandard("LVCMOS33")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("C23")),
Subsignal("mosi", Pins("B24")),
Subsignal("miso", Pins("A25")),
Subsignal("wp", Pins("B22")),
Subsignal("hold", Pins("A22")),
IOStandard("LVCMOS33"),
),
("mmc", 0,
Subsignal("cmd", Pins("H24")),
Subsignal("clk", Pins("G22")),
Subsignal("dat", Pins("F25 E25 J23 H23")),
IOStandard("LVCMOS33")
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("K6")),
Subsignal("clk_n", Pins("K5")),
Subsignal("rx_p", Pins("J4")),
Subsignal("rx_n", Pins("J3")),
Subsignal("tx_p", Pins("H2")),
Subsignal("tx_n", Pins("H1"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("K6")),
Subsignal("clk_n", Pins("K5")),
Subsignal("rx_p", Pins("J4 L4")),
Subsignal("rx_n", Pins("J3 L3")),
Subsignal("tx_p", Pins("H2 K2")),
Subsignal("tx_n", Pins("H1 K1"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("K6")),
Subsignal("clk_n", Pins("K5")),
Subsignal("rx_p", Pins("J4 L4 N4 R4")),
Subsignal("rx_n", Pins("J3 L3 N3 R3")),
Subsignal("tx_p", Pins("H2 K2 M2 P2")),
Subsignal("tx_n", Pins("H1 K1 M1 P1"))
),
]
_connectors = [
("HPC", {
# FMC GTP Section
"DP0_M2C_P": "G4",
"DP0_M2C_N": "G3",
"DP1_M2C_P": "E4",
"DP1_M2C_N": "E3",
"DP2_M2C_P": "C4",
"DP2_M2C_N": "C3",
"DP3_M2C_P": "B6",
"DP3_M2C_N": "B5",
"GBTCLK0_M2C_P": "F6",
"GBTCLK0_M2C_N": "F5",
"GBTCLK1_M2C_P": "D6",
"GBTCLK1_M2C_N": "D5",
"DP0_C2M_P": "F2",
"DP0_C2M_N": "F1",
"DP1_C2M_P": "D2",
"DP1_C2M_N": "D1",
"DP2_C2M_P": "B2",
"DP2_C2M_N": "B1",
"DP3_C2M_P": "A4",
"DP3_C2M_N": "A3",
# FMC LA Bank GPIOs
"LA00_P": "AA23",
"LA00_N": "AB24",
"LA01_P": "Y23",
"LA01_N": "AA24",
"LA02_P": "AD26",
"LA02_N": "AE26",
"LA03_P": "AA25",
"LA03_N": "AB25",
"LA04_P": "AD25",
"LA04_N": "AE25",
"LA05_P": "W25",
"LA05_N": "W26",
"LA06_P": "Y25",
"LA06_N": "Y26",
"LA07_P": "V23",
"LA07_N": "V24",
"LA08_P": "U26",
"LA08_N": "V26",
"LA09_P": "W20",
"LA09_N": "Y21",
"LA10_P": "V21",
"LA10_N": "W21",
"LA11_P": "L19",
"LA11_N": "L20",
"LA12_P": "M17",
"LA12_N": "L18",
"LA13_P": "K20",
"LA13_N": "J20",
"LA14_P": "J18",
"LA14_N": "J19",
"LA15_P": "U17",
"LA15_N": "T17",
"LA16_P": "T18",
"LA16_N": "T19",
"LA17_P": "E18",
"LA17_N": "D18",
"LA18_P": "F17",
"LA18_N": "E17",
"LA19_P": "H16",
"LA19_N": "G16",
"LA20_P": "K16",
"LA20_N": "K17",
"LA21_P": "D19",
"LA21_N": "D20",
"LA22_P": "C19",
"LA22_N": "B19",
"LA23_P": "C17",
"LA23_N": "C18",
"LA24_P": "D15",
"LA24_N": "D16",
"LA25_P": "F19",
"LA25_N": "E20",
"LA26_P": "J15",
"LA26_N": "J16",
"LA27_P": "G15",
"LA27_N": "F15",
"LA28_P": "G17",
"LA28_N": "F18",
"LA29_P": "E15",
"LA29_N": "E16",
"LA30_P": "H17",
"LA30_N": "H18",
"LA31_P": "G19",
"LA31_N": "F20",
"LA32_P": "H19",
"LA32_N": "G20",
"LA33_P": "L17",
"LA33_N": "K18",
# FMC HA Bank GPIOs
"HA00_P": "P23",
"HA00_N": "N23",
"HA01_P": "N21",
"HA01_N": "N22",
"HA02_P": "AB22",
"HA02_N": "AC22",
"HA03_P": "AD23",
"HA03_N": "AD24",
"HA04_P": "N19",
"HA04_N": "M20",
"HA05_P": "R18",
"HA05_N": "P18",
"HA06_P": "P16",
"HA06_N": "N17",
"HA07_P": "R16",
"HA07_N": "R17",
"HA08_P": "U19",
"HA08_N": "U20",
"HA09_P": "N18",
"HA09_N": "M19",
"HA10_P": "T20",
"HA10_N": "R20",
"HA11_P": "P19",
"HA11_N": "P20",
"HA12_P": "T24",
"HA12_N": "T25",
"HA13_P": "U24",
"HA13_N": "U25",
"HA14_P": "R26",
"HA14_N": "P26",
"HA15_P": "P24",
"HA15_N": "N24",
"HA16_P": "R25",
"HA16_N": "P25",
"HA17_P": "M21",
"HA17_N": "M22",
"HA18_P": "N26",
"HA18_N": "M26",
"HA19_P": "K25",
"HA19_N": "K26",
"HA20_P": "M25",
"HA20_N": "L25",
"HA21_P": "M24",
"HA21_N": "L24",
"HA22_P": "T22",
"HA22_N": "T23",
"HA23_P": "U22",
"HA23_N": "V22",
# FMC HB Bank GPIOs
"HB00_P": "E10",
"HB00_N": "D10",
"HB01_P": "F14",
"HB01_N": "F13",
"HB02_P": "H14",
"HB02_N": "G14",
"HB03_P": "J13",
"HB03_N": "H13",
"HB04_P": "B14",
"HB04_N": "A14",
"HB05_P": "B15",
"HB05_N": "A15",
"HB06_P": "C12",
"HB06_N": "C11",
"HB07_P": "G10",
"HB07_N": "G9",
"HB08_P": "E13",
"HB08_N": "E12",
"HB09_P": "D14",
"HB09_N": "D13",
"HB10_P": "C9",
"HB10_N": "B9",
"HB11_P": "A13",
"HB11_N": "A12",
"HB12_P": "B10",
"HB12_N": "A10",
"HB13_P": "B12",
"HB13_N": "B11",
"HB14_P": "F9",
"HB14_N": "F8",
"HB15_P": "E11",
"HB15_N": "D11",
"HB16_P": "D9",
"HB16_N": "D8",
"HB17_P": "G11",
"HB17_N": "F10",
"HB18_P": "G12",
"HB18_N": "F12",
"HB19_P": "A9",
"HB19_N": "A8",
"HB20_P": "J11",
"HB20_N": "J10",
"HB21_P": "H9",
"HB21_N": "H8",
# FMC Clock and Misc signals
"CLK0_M2C_P": "Y22",
"CLK0_M2C_N": "AA22",
"CLK1_M2C_P": "AC23",
"CLK1_M2C_N": "AC24",
"CLK2_BIDIR_P": "R22",
"CLK2_BIDIR_N": "R23",
"CLK3_BIDIR_P": "R21",
"CLK3_BIDIR_N": "P21",
"CLK_DIR": "D23",
"PG_C2M": "D26",
"PG_M2C": "E26",
"FMC_SCL": "C21",
"FMC_SDA": "B21",
"FMC_PRSNT": "B26",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k160t-fbg676-1", _io, _connectors,
toolchain=toolchain)
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
""")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
def create_programmer(self):
if self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported".format(self.programmer))

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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clk / rst
("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")),
("rst", 0, Pins("P17"), IOStandard("LVCMOS33")),
# leds (only a single rgb led, aliased here also)
("user_led", 0, Pins("W21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("W22"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("AA20"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("W21")),
Subsignal("g", Pins("W22")),
Subsignal("b", Pins("AA20")),
IOStandard("LVCMOS33"),
),
("serial", 0,
Subsignal("tx", Pins("R14")),
Subsignal("rx", Pins("P14")),
Subsignal("rts", Pins("R18")),
Subsignal("cts", Pins("T18")),
Subsignal("cbus0", Pins("N17")),
IOStandard("LVCMOS33")
),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("vvp", Pins("P21")),
Subsignal("hold", Pins("R21")),
IOStandard("LVCMOS33")
),
("flash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("T19")),
Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
IOStandard("LVCMOS33")
),
# tpm
("tpm", 0,
Subsignal("clk", Pins("Y18")),
Subsignal("rst_n", Pins("AA19")),
Subsignal("cs_n", Pins("Y19")),
Subsignal("mosi", Pins("V18")),
Subsignal("miso", Pins("V19")),
IOStandard("LVCMOS33"),
),
# pcie
("pcie_x1", 0,
Subsignal("rst_n", Pins("W20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8")),
Subsignal("rx_n", Pins("A8")),
Subsignal("tx_p", Pins("B4")),
Subsignal("tx_n", Pins("A4"))
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 T5 Y6 T6 V2 T4 Y2 R2",
"Y1 R4 W5 W1 AA6 U2"
),
IOStandard("SSTL15")),
Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y7 K1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
"H4 G2 J5 H2 H5 G4 J1 G3"
),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("V9 K2"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("V8 J2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("U7"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
# sdcard
("sdcard", 0,
Subsignal("data", Pins("P19 Y22 Y21 T21")),
Subsignal("cmd", Pins("U21")),
Subsignal("clk", Pins("R19")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
# sfp0
("sfp_tx", 0,
Subsignal("p", Pins("B6")),
Subsignal("n", Pins("A6"))
),
("sfp_rx", 0,
Subsignal("p", Pins("B10")),
Subsignal("n", Pins("A10"))
),
("sfp_tx_disable_n", 0, Pins("V22"), IOStandard("LVCMOS33")),
("sfp_rx_los", 0, Pins("AB21"), IOStandard("LVCMOS33")),
# sfp1
("sfp_tx", 1,
Subsignal("p", Pins("D7")),
Subsignal("n", Pins("C7"))
),
("sfp_rx", 1,
Subsignal("p", Pins("D9")),
Subsignal("n", Pins("C9"))
),
("sfp_tx_disable_n", 1, Pins("P15"), IOStandard("LVCMOS33")),
("sfp_rx_los", 1, Pins("R17"), IOStandard("LVCMOS33")),
]
# TODO: Add complete LPC IOs
_connectors = [
("LPC", {
# FMC GTP Section
"DP0_M2C_P": "D11",
"DP0_M2C_N": "C11",
"GBTCLK0_M2C_P": "F10",
"GBTCLK0_M2C_N": "E10",
"DP0_C2M_P": "D5",
"DP0_C2M_N": "C5",
}
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]

3
litex_boards/partner/targets/__init__.py
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@ -1,3 +1,6 @@
#from litex_boards.partner.targets import aller
#from litex_boards.partner.targets import nereid
#from litex_boards.partner.targets import netv2
#from litex_boards.partner.targets import tagus
#from litex_boards.partner.targets import trellisboard
#from litex_boards.partner.targets import ulx3s

209
litex_boards/partner/targets/aller.py Executable file
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#!/usr/bin/env python3
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
# License: BSD
import sys
from migen import *
from litex.build.generic_platform import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.clock import *
from litex.soc.cores import dna, xadc
from litex.soc.cores.uart import *
from litex.soc.integration.cpu_interface import get_csr_header
from litedram.modules import MT41J128M16
from litedram.phy import s7ddrphy
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
from litex_boards.platforms import aller
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
clk100 = platform.request("clk100")
self.submodules.pll = pll = S7PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# AllerSoC ------------------------------------------------------------------------------------------
class AllerSoC(SoCSDRAM):
SoCSDRAM.mem_map["csr"] = 0x00000000
SoCSDRAM.mem_map["rom"] = 0x20000000
def __init__(self, platform, with_pcie_uart=True):
sys_clk_freq = int(100e6)
# soc sdram
# ------------------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq,
csr_data_width=32,
integrated_rom_size=0x10000,
integrated_sram_size=0x10000,
integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests
ident="Aller LiteX Test SoC", ident_version=True,
with_uart=not with_pcie_uart)
# crg
# ------------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# dna
# ------------------------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# xadc
# ------------------------------------------------------------------------------------------
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# sdram
# ------------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.add_csr("ddrphy")
# pcie
# ------------------------------------------------------------------------------------------
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base)
self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering=True, buffering_depth=1024, with_loopback=True)
self.add_csr("pcie_dma")
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.msis = {
"DMA_WRITER": self.pcie_dma.writer.irq,
"DMA_READER": self.pcie_dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# pcie_uart
# ------------------------------------------------------------------------------------------
if with_pcie_uart:
class PCIeUART(Module, AutoCSR):
def __init__(self, uart):
self.rx_valid = CSRStatus()
self.rx_ready = CSR()
self.rx_data = CSRStatus(8)
self.tx_valid = CSR()
self.tx_ready = CSRStatus()
self.tx_data = CSRStorage(8)
# # #
# cpu to pcie
self.comb += [
self.rx_valid.status.eq(uart.sink.valid),
uart.sink.ready.eq(self.rx_ready.re),
self.rx_data.status.eq(uart.sink.data),
]
# pcie to cpu
self.sync += [
If(self.tx_valid.re,
uart.source.valid.eq(1)
).Elif(uart.source.ready,
uart.source.valid.eq(0)
)
]
self.comb += [
self.tx_ready.status.eq(~uart.source.valid),
uart.source.data.eq(self.tx_data.storage)
]
uart_interface = RS232PHYInterface()
self.submodules.uart = UART(uart_interface)
self.add_csr("uart")
self.add_interrupt("uart")
self.submodules.pcie_uart = PCIeUART(uart_interface)
self.add_csr("pcie_uart")
# leds
# ------------------------------------------------------------------------------------------
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += [
platform.request("user_led", 0).eq(~self.pcie_phy._lnk_up.status),
platform.request("user_led", 1).eq(~pcie_counter[26]),
platform.request("user_led", 2).eq(~sys_counter[26]),
]
def generate_software_header(self, filename):
csr_header = get_csr_header(self.get_csr_regions(),
self.get_constants(),
with_access_functions=False,
with_shadow_base=False)
tools.write_to_file(filename, csr_header)
# Build --------------------------------------------------------------------------------------------
def main():
platform = aller.Platform()
soc = AllerSoC(platform)
builder = Builder(soc, output_dir="../build/aller", csr_csv="../build/aller/csr.csv",
compile_gateware=not "no-compile" in sys.argv[1:])
vns = builder.build(build_name="aller")
soc.generate_software_header("../software/kernel/csr.h")
if __name__ == "__main__":
main()

224
litex_boards/partner/targets/nereid.py Executable file
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#!/usr/bin/env python3
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
# License: BSD
import sys
from migen import *
from litex.build.generic_platform import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.clock import *
from litex.soc.cores import dna, xadc
from litex.soc.cores.uart import *
from litex.soc.integration.cpu_interface import get_csr_header
from litedram.modules import SDRAMModule
from litedram.modules import _TechnologyTimings, _SpeedgradeTimings
from litedram.phy import s7ddrphy
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
from litex_boards.platforms import nereid
# sdram module
# --------------------------------------------------------------------------------------------------
class MT8KTF51264(SDRAMModule):
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10))
speedgrade_timings = {
"800": _SpeedgradeTimings(tRP=13.91, tRCD=13.91, tWR=13.91, tRFC=260, tFAW=(None, 50), tRAS=None),
"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=86, tFAW=(None, 50), tRAS=None),
"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=107, tFAW=(None, 45), tRAS=None),
}
speedgrade_timings["default"] = speedgrade_timings["1333"]
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
clk100 = platform.request("clk100")
self.submodules.pll = pll = S7PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_clk200, 200e6)
self.comb += pll.reset.eq(platform.request("cpu_reset"))
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# NereidSoC ------------------------------------------------------------------------------------------
class NereidSoC(SoCSDRAM):
SoCSDRAM.mem_map["csr"] = 0x00000000
SoCSDRAM.mem_map["rom"] = 0x20000000
def __init__(self, platform, with_pcie_uart=True):
sys_clk_freq = int(100e6)
# soc sdram
# ------------------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq,
csr_data_width=32,
integrated_rom_size=0x10000,
integrated_sram_size=0x10000,
integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests
ident="Nereid LiteX Test SoC", ident_version=True,
with_uart=not with_pcie_uart)
# crg
# ------------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# dna
# ------------------------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# xadc
# ------------------------------------------------------------------------------------------
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# sdram
# ------------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
sdram_module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.add_csr("ddrphy")
# pcie
# ------------------------------------------------------------------------------------------
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base)
self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering=True, buffering_depth=1024, with_loopback=True)
self.add_csr("pcie_dma")
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.msis = {
"DMA_WRITER": self.pcie_dma.writer.irq,
"DMA_READER": self.pcie_dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# pcie_uart
# ------------------------------------------------------------------------------------------
if with_pcie_uart:
class PCIeUART(Module, AutoCSR):
def __init__(self, uart):
self.rx_valid = CSRStatus()
self.rx_ready = CSR()
self.rx_data = CSRStatus(8)
self.tx_valid = CSR()
self.tx_ready = CSRStatus()
self.tx_data = CSRStorage(8)
# # #
# cpu to pcie
self.comb += [
self.rx_valid.status.eq(uart.sink.valid),
uart.sink.ready.eq(self.rx_ready.re),
self.rx_data.status.eq(uart.sink.data),
]
# pcie to cpu
self.sync += [
If(self.tx_valid.re,
uart.source.valid.eq(1)
).Elif(uart.source.ready,
uart.source.valid.eq(0)
)
]
self.comb += [
self.tx_ready.status.eq(~uart.source.valid),
uart.source.data.eq(self.tx_data.storage)
]
uart_interface = RS232PHYInterface()
self.submodules.uart = UART(uart_interface)
self.add_csr("uart")
self.add_interrupt("uart")
self.submodules.pcie_uart = PCIeUART(uart_interface)
self.add_csr("pcie_uart")
# leds
# ------------------------------------------------------------------------------------------
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
rgb = platform.request("rgb_led")
self.comb += [
rgb.r.eq(1),
rgb.g.eq(sys_counter[26]),
rgb.b.eq(1),
]
def generate_software_header(self, filename):
csr_header = get_csr_header(self.get_csr_regions(),
self.get_constants(),
with_access_functions=False,
with_shadow_base=False)
tools.write_to_file(filename, csr_header)
# Build --------------------------------------------------------------------------------------------
def main():
platform = nereid.Platform()
soc = NereidSoC(platform)
builder = Builder(soc, output_dir="../build/nereid", csr_csv="../build/nereid/csr.csv",
compile_gateware=not "no-compile" in sys.argv[1:])
vns = builder.build(build_name="nereid")
soc.generate_software_header("../software/kernel/csr.h")
if __name__ == "__main__":
main()

206
litex_boards/partner/targets/tagus.py Executable file
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#!/usr/bin/env python3
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
# License: BSD
import sys
from migen import *
from litex.build.generic_platform import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.clock import *
from litex.soc.cores import dna, xadc
from litex.soc.cores.uart import *
from litex.soc.integration.cpu_interface import get_csr_header
from litedram.modules import MT41J128M16
from litedram.phy import s7ddrphy
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
from litex_boards.platforms import tagus
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
clk100 = platform.request("clk100")
self.submodules.pll = pll = S7PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
self.comb += pll.reset.eq(platform.request("rst"))
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# NereidSoC ------------------------------------------------------------------------------------------
class TagusSoC(SoCSDRAM):
SoCSDRAM.mem_map["csr"] = 0x00000000
SoCSDRAM.mem_map["rom"] = 0x20000000
def __init__(self, platform, with_pcie_uart=True):
sys_clk_freq = int(100e6)
# soc sdram
# ------------------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq,
csr_data_width=32,
integrated_rom_size=0x10000,
integrated_sram_size=0x10000,
integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests
ident="Tagus LiteX Test SoC", ident_version=True,
with_uart=not with_pcie_uart)
# crg
# ------------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# dna
# ------------------------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# xadc
# ------------------------------------------------------------------------------------------
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# sdram
# ------------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.add_csr("ddrphy")
# pcie
# ------------------------------------------------------------------------------------------
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
self.pcie_phy.cd_pcie.clk.attr.add("keep")
platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=self.shadow_base)
self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering=True, buffering_depth=1024, with_loopback=True)
self.add_csr("pcie_dma")
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.msis = {
"DMA_WRITER": self.pcie_dma.writer.irq,
"DMA_READER": self.pcie_dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# pcie_uart
# ------------------------------------------------------------------------------------------
if with_pcie_uart:
class PCIeUART(Module, AutoCSR):
def __init__(self, uart):
self.rx_valid = CSRStatus()
self.rx_ready = CSR()
self.rx_data = CSRStatus(8)
self.tx_valid = CSR()
self.tx_ready = CSRStatus()
self.tx_data = CSRStorage(8)
# # #
# cpu to pcie
self.comb += [
self.rx_valid.status.eq(uart.sink.valid),
uart.sink.ready.eq(self.rx_ready.re),
self.rx_data.status.eq(uart.sink.data),
]
# pcie to cpu
self.sync += [
If(self.tx_valid.re,
uart.source.valid.eq(1)
).Elif(uart.source.ready,
uart.source.valid.eq(0)
)
]
self.comb += [
self.tx_ready.status.eq(~uart.source.valid),
uart.source.data.eq(self.tx_data.storage)
]
uart_interface = RS232PHYInterface()
self.submodules.uart = UART(uart_interface)
self.add_csr("uart")
self.add_interrupt("uart")
self.submodules.pcie_uart = PCIeUART(uart_interface)
self.add_csr("pcie_uart")
# leds
# ------------------------------------------------------------------------------------------
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += [
platform.request("user_led", 0).eq(1),
platform.request("user_led", 1).eq(sys_counter[26]),
platform.request("user_led", 2).eq(1),
]
def generate_software_header(self, filename):
csr_header = get_csr_header(self.get_csr_regions(),
self.get_constants(),
with_access_functions=False,
with_shadow_base=False)
tools.write_to_file(filename, csr_header)
# Build --------------------------------------------------------------------------------------------
def main():
platform = tagus.Platform()
soc = TagusSoC(platform)
builder = Builder(soc, output_dir="../build/tagus", csr_csv="../build/tagus/csr.csv",
compile_gateware=not "no-compile" in sys.argv[1:])
vns = builder.build(build_name="tagus")
soc.generate_software_header("../software/kernel/csr.h")
if __name__ == "__main__":
main()