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targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build)

This commit is contained in:
Florent Kermarrec 2019-11-01 10:52:36 +01:00
parent 1ae26dd499
commit 5bd8c4d74f
1 changed files with 7 additions and 1 deletions
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8
litex_boards/partner/targets/trellisboard.py
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@ -55,13 +55,19 @@ class _CRG(Module):
self.sync.por += If(~por_done, por_count.eq(por_count - 1)) self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll # pll
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk12, 12e6) pll.register_clkin(clk12, 12e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6) pll.create_clkout(self.cd_init, 25e6)
self.specials += [ self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0=self.cd_sys2x_i.clk,
i_SEL=0,
o_ECSOUT=sys2x_clk_ecsout,
),
Instance("ECLKSYNCB", Instance("ECLKSYNCB",
i_ECLKI=self.cd_sys2x_i.clk, i_ECLKI=sys2x_clk_ecsout,
i_STOP=self.stop, i_STOP=self.stop,
o_ECLKO=self.cd_sys2x.clk), o_ECLKO=self.cd_sys2x.clk),
Instance("CLKDIVF", Instance("CLKDIVF",