platforms/sipeed_tang_primer_25k: swap UART TX & RX, fix TX pin (J1:20 -> J1:21)

2023-10-19 06:26:10 +02:00 · 2023-10-19 06:26:10 +02:00 · 5f694166ce
parent a4fc45bba6
commit 5f694166ce
1 changed files with 2 additions and 2 deletions
--- a/litex_boards/platforms/sipeed_tang_primer_25k.py
+++ b/litex_boards/platforms/sipeed_tang_primer_25k.py
@ -75,8 +75,8 @@ _connectors = [
 _dock_io = [
    # Serial.
    ("serial", 0,
-        Subsignal("rx", Pins("J1:20")),
-        Subsignal("tx", Pins("J1:19")),
+        Subsignal("rx", Pins("J1:19")),
+        Subsignal("tx", Pins("J1:21")),
        IOStandard("LVCMOS33")
    ),