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Update ecp5_evn.py 

The system clock was driven directly while it should be driven by the PLL.
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Arnaud Durand 2019-08-22 02:27:50 +02:00 committed by GitHub
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commit 618f41bb1e
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litex_boards/community/targets/ecp5_evn.py
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@ -39,7 +39,6 @@ class _CRG(Module):
pll.register_clkin(clk, x5_clk_freq or 12e6) pll.register_clkin(clk, x5_clk_freq or 12e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
self.comb += self.cd_sys.clk.eq(clk)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------