Update ecp5_evn.py

The system clock was driven directly while it should be driven by the PLL.
2019-08-22 02:27:50 +02:00 · 2019-08-22 02:27:50 +02:00 · 618f41bb1e
parent e31360b1c6
commit 618f41bb1e
1 changed files with 0 additions and 1 deletions
--- a/litex_boards/community/targets/ecp5_evn.py
+++ b/litex_boards/community/targets/ecp5_evn.py
@ -39,7 +39,6 @@ class _CRG(Module):
        pll.register_clkin(clk, x5_clk_freq or 12e6)
        pll.create_clkout(self.cd_sys, sys_clk_freq)
        self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
-        self.comb += self.cd_sys.clk.eq(clk)

 # BaseSoC ------------------------------------------------------------------------------------------