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Merge pull request #465 from gatecat/vip-fix 

nx_vip: Add missing 'origin' to SRAM SocRegions
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enjoy-digital 2023-01-04 19:51:11 +01:00 committed by GitHub
parent f5643e7c78 764f64ff1e
commit 6658f20682
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1 changed files with 4 additions and 2 deletions
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litex_boards/targets/lattice_crosslink_nx_vip.py
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@ -84,13 +84,15 @@ class BaseSoC(SoCCore):
# 128KB LRAM (used as SRAM) ------------------------------------------------------------
size = 128*kB
self.spram = NXLRAM(32, size)
self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(size=size))
self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(origin=self.mem_map["sram"],
size=size))
else:
# Use HyperRAM generic PHY as SRAM -----------------------------------------------------
size = 8*1024*kB
hr_pads = platform.request("hyperram", int(hyperram))
self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size))
self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"],
size=size))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser: