sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs

2021-11-29 11:46:32 +01:00 · 2021-11-29 11:46:32 +01:00 · 666ef9dad3
parent 2fb734a0f2
commit 666ef9dad3
1 changed files with 3 additions and 0 deletions
--- a/litex_boards/targets/sipeed_tang_nano_4k.py
+++ b/litex_boards/targets/sipeed_tang_nano_4k.py
@ -72,6 +72,9 @@ class BaseSoC(SoCCore):
        kwargs["integrated_rom_size"] = 0
        kwargs["cpu_reset_address"]   = self.mem_map["spiflash"] + 0

+        kwargs["cpu_type"] = 'vexriscv'
+        kwargs["cpu_variant"] = 'minimal'
+
        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident         = "LiteX SoC on Tang Nano 4K",