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sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs

This commit is contained in:
Ilia Sergachev 2021-11-29 11:46:32 +01:00
parent 2fb734a0f2
commit 666ef9dad3
1 changed files with 3 additions and 0 deletions
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litex_boards/targets/sipeed_tang_nano_4k.py
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@ -72,6 +72,9 @@ class BaseSoC(SoCCore):
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0 kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0
kwargs["cpu_type"] = 'vexriscv'
kwargs["cpu_variant"] = 'minimal'
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Tang Nano 4K", ident = "LiteX SoC on Tang Nano 4K",