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targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands. 

This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.

Also remove un-needed cd_sys2x_eb.
This commit is contained in:
Florent Kermarrec 2021-01-12 18:56:58 +01:00
parent 9ff90eb9fe
commit 6a5f2f59a6
1 changed files with 1 additions and 1 deletions
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litex_boards/targets/orangecrab.py
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@ -81,7 +81,6 @@ class _CRGSDRAM(Module):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
# # # # # #
@ -183,6 +182,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = ECP5DDRPHY( self.submodules.ddrphy = ECP5DDRPHY(
pads = ddram_pads, pads = ddram_pads,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
cmd_delay = 0 if sys_clk_freq > 64e6 else 100,
dm_remapping = {0:1, 1:0}) dm_remapping = {0:1, 1:0})
self.ddrphy.settings.rtt_nom = "disabled" self.ddrphy.settings.rtt_nom = "disabled"
self.add_csr("ddrphy") self.add_csr("ddrphy")