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platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance.

This commit is contained in:
Florent Kermarrec 2021-01-29 08:41:10 +01:00
parent 4eb5533040
commit 6c6d8a1393
1 changed files with 56 additions and 57 deletions
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29
litex_boards/platforms/fpc_iii.py
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@ -26,11 +26,6 @@ _io = [
("user_led", 6, Pins("T20"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
("user_led", 7, Pins("D6"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
# Serial
#("serial", 0,
# Subsignal("rx", Pins("N2"), IOStandard("LVCMOS33")),
# Subsignal("tx", Pins("M1"), IOStandard("LVCMOS33"))),
# USB FIFO
("usb_fifo", 0,
Subsignal( "data", Pins("N2 M1 M3 L1 L2 K1 K2 J1")),
@ -85,8 +80,10 @@ _io = [
# DDR3 SDRAM
("dram_vtt_en", 0, Pins("M19"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
("ddram", 0,
Subsignal( "a", Pins( "E18 H16 D18 L16 H17 E17 G18 C18 "
"G16 D17 J16 F18 J17 F16 F17" ),
Subsignal("a", Pins(
"E18 H16 D18 L16 H17 E17 G18 C18 "
"G16 D17 J16 F18 J17 F16 F17"
),
IOStandard("SSTL15_I")),
Subsignal("ba", Pins("M18 H18 L17"), IOStandard("SSTL15_I")),
Subsignal("ras_n", Pins("R17"), IOStandard("SSTL15_I")),
@ -94,17 +91,19 @@ _io = [
Subsignal("we_n", Pins("M17"), IOStandard("SSTL15_I")),
Subsignal("cs_n", Pins("P17"), IOStandard("SSTL15_I")),
Subsignal("dm", Pins("F20 T18"), IOStandard("SSTL15_I")),
Subsignal( "dq", Pins( "J20 F19 J19 E19 K19 E20 K20 G20 ",
Subsignal("dq", Pins(
"J20 F19 J19 E19 K19 E20 K20 G20",
"T17 U16 P18 U17 N19 U18 P19 U19"),
IOStandard( "SSTL15_I" ), Misc( "TERMINATION=50" ) ),
IOStandard("SSTL15_I"),
Misc("TERMINATION=50")),
Subsignal("dqs_p", Pins("G19 T19"), IOStandard("SSTL15D_I"),
Misc( "TERMINATION=OFF" ), Misc( "DIFFRESISTOR=100" ) ),
Misc("TERMINATION=OFF"),
Misc("DIFFRESISTOR=100")),
Subsignal("clk_p" , Pins("K16"), IOStandard("SSTL15D_I")),
Subsignal("cke", Pins("D19"), IOStandard("SSTL15_I")),
Subsignal("odt", Pins("H4")), # FIXME not connected
Subsignal("reset_n", Pins("L20"), IOStandard("SSTL15_I")),
# Pseudo-VCCIO pads: SSTL15_II for 10 mA drive strength, see
# FPGA-TN-02035, section 6.7.
# Pseudo-VCCIO pads: SSTL15_II for 10 mA drive strength, see FPGA-TN-02035, section 6.7.
Subsignal( "vccio", Pins( "C20 E16 J18 K18 L18 L19 N17 N18 T16" ),
IOStandard( "SSTL15_II" ) ),
Misc("SLEWRATE=FAST")),
@ -134,7 +133,8 @@ _io = [
Subsignal("data1", Pins("F4")),
Subsignal("data2", Pins("C1")),
Subsignal("clk", Pins("E4") ),
IOStandard( "LVCMOS33D" ), Misc( "DRIVE=8 SLEWRATE=FAST" ) ),
IOStandard("LVCMOS33D"),
Misc("DRIVE=8 SLEWRATE=FAST")),
# USB host 1
("usbhost", 0,
@ -145,8 +145,7 @@ _io = [
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
]
_connectors = []
# Platform -----------------------------------------------------------------------------------------