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Added DFU support to Butterstick

This commit is contained in:
Adam Zeloof 2022-09-10 17:45:57 +01:00
parent 756e4f73fc
commit 6d0a4c788e
2 changed files with 11 additions and 5 deletions
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12
litex_boards/platforms/gsd_butterstick.py
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@ -4,10 +4,11 @@
# Copyright (c) 2021 Greg Davill <greg.davill@gmail.com> # Copyright (c) 2021 Greg Davill <greg.davill@gmail.com>
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import OpenOCDJTAGProgrammer from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
from litex.build.dfu import DFUProg
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
@ -194,8 +195,13 @@ class Platform(LatticePlatform):
connectors = {"1.0": _connectors_r1_0}[revision] connectors = {"1.0": _connectors_r1_0}[revision]
LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs) LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs)
def create_programmer(self): def create_programmer(self, load):
return OpenOCDJTAGProgrammer("openocd_butterstick.cfg") if load == "jtag":
return OpenOCDJTAGProgrammer("openocd_butterstick.cfg")
elif load == "dfu":
return DFUProg(vid="1209", pid="5af1", alt=0)
else:
print("Could not program board. "+load+" is not a valid argument. Please use 'jtag' or 'dfu'.")
def do_finalize(self, fragment): def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment) LatticePlatform.do_finalize(self, fragment)

4
litex_boards/targets/gsd_butterstick.py
View File

@ -155,7 +155,7 @@ def main():
parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick") parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick")
target_group = parser.add_argument_group(title="Target options") target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.") target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--load", default="jtag", help="Load bitstream (jtag or dfu).")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).") target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--revision", default="1.0", help="Board Revision (1.0).") target_group.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
@ -201,7 +201,7 @@ def main():
builder.build(**builder_kargs) builder.build(**builder_kargs)
if args.load: if args.load:
prog = soc.platform.create_programmer() prog = soc.platform.create_programmer(args.load)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__": if __name__ == "__main__":