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Merge pull request #524 from josuah/crosslink_nx_main_ram 

targets/lattice_crosslink_nx_evn: add main_ram section for firmware
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enjoy-digital 2023-08-28 16:34:34 +02:00 committed by GitHub
parent a9ecbffe8f 232e829b8f
commit 6e7f58f2df
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1 changed files with 10 additions and 6 deletions
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litex_boards/targets/lattice_crosslink_nx_evn.py
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@ -63,10 +63,12 @@ class _CRG(LiteXModule):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
mem_map = { mem_map = {
"rom" : 0x00000000, "rom" : 0x00000000,
"sram" : 0x40000000, "sram" : 0x40000000,
"csr" : 0xf0000000, "main_ram" : 0x60000000,
"csr" : 0xf0000000,
} }
def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant", def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant",
with_led_chaser = True, with_led_chaser = True,
with_spi_flash = False, with_spi_flash = False,
@ -85,9 +87,11 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
# 128KB LRAM (used as SRAM) --------------------------------------------------------------- # 128KB LRAM (used as SRAM) ---------------------------------------------------------------
size = 128*kB self.spram = NXLRAM(32, 64*kB)
self.spram = NXLRAM(32, size) self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=size))
self.main_ram = NXLRAM(32, 64*kB)
self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser: