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ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.

This commit is contained in:
Florent Kermarrec 2020-08-24 09:05:27 +02:00
parent 1781be166a
commit 70594a5305
2 changed files with 3 additions and 10 deletions
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11
litex_boards/platforms/ulx3s.py
View File

@ -45,12 +45,7 @@ _io = [
IOStandard("LVCMOS33"),
),
("sdram_clock", 0, Pins("F19"),
Misc("PULLMODE=NONE"),
Misc("DRIVE=4"),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33")
),
("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"M20 M19 L20 L19 K20 K19 K18 J20",
@ -65,10 +60,8 @@ _io = [
Subsignal("cke", Pins("F20")),
Subsignal("ba", Pins("P19 N20")),
Subsignal("dm", Pins("U19 E20")),
Misc("PULLMODE=NONE"),
Misc("DRIVE=4"),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
Misc("SLEWRATE=FAST"),
),
("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),

2
litex_boards/targets/ulx3s.py
View File

@ -55,7 +55,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)