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targets: --no-ident-version is now directly provided by LiteX, remove it on targets implementing it.

This commit is contained in:
Florent Kermarrec 2022-01-18 16:47:38 +01:00
parent d92a2b82fb
commit 7114911cea
8 changed files with 8 additions and 34 deletions
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5
litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
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@ -52,13 +52,12 @@ class BaseSoC(SoCCore):
def __init__(self, *, sys_clk_freq=int(100e6), iodelay_clk_freq=200e6,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
with_led_chaser=True, ident_version=True, eth_reset_time, **kwargs):
with_led_chaser=True, eth_reset_time, **kwargs):
platform = datacenter_ddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on data center test board",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -135,7 +134,6 @@ def main():
target.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
target.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
target.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
@ -155,7 +153,6 @@ def main():
with_sdcard = args.with_sdcard,
with_jtagbone = args.with_jtagbone,
with_uartbone = args.with_uartbone,
ident_version = args.no_ident_version,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build(**vivado_build_argdict(args), run=args.build)

5
litex_boards/targets/antmicro_lpddr4_test_board.py
View File

@ -51,13 +51,12 @@ class BaseSoC(SoCCore):
def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
with_led_chaser=True, ident_version=True, **kwargs):
with_led_chaser=True, **kwargs):
platform = lpddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on LPDDR4 Test Board",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -133,7 +132,6 @@ def main():
target.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
target.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
target.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
@ -152,7 +150,6 @@ def main():
with_sdcard = args.with_sdcard,
with_jtagbone = args.with_jtagbone,
with_uartbone = args.with_uartbone,
ident_version = args.no_ident_version,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build(**vivado_build_argdict(args), run=args.build)

5
litex_boards/targets/digilent_arty.py
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@ -62,14 +62,13 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
eth_dynamic_ip=False, ident_version=True, with_led_chaser=True, with_jtagbone=True,
eth_dynamic_ip=False, with_led_chaser=True, with_jtagbone=True,
with_spi_flash=False, with_pmod_gpio=False, **kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -136,7 +135,6 @@ def main():
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter (digilent or numato).")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output.")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
@ -155,7 +153,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
ident_version = args.no_ident_version,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_pmod_gpio = args.with_pmod_gpio,

6
litex_boards/targets/qmtech_10cl006.py
View File

@ -67,7 +67,7 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
ident_version=True, sdram_rate="1:1", **kwargs):
sdram_rate="1:1", **kwargs):
platform = qmtech_10cl006.Platform(with_daughterboard=with_daughterboard)
# unfornunately not even SERV would fit the devices
@ -80,7 +80,6 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTECH 10CL006" + (" + Daughterboard" if with_daughterboard else ""),
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -117,8 +116,6 @@ def main():
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--no-ident-version", action="store_false",help="Disable build time output.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
@ -126,7 +123,6 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_daughterboard = args.with_daughterboard,
ident_version = args.no_ident_version,
with_spi_flash = args.with_spi_flash,
sdram_rate = args.sdram_rate,
**soc_core_argdict(args)

6
litex_boards/targets/qmtech_5cefa2.py
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@ -80,13 +80,12 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(105e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
ident_version=True, sdram_rate="1:1", **kwargs):
sdram_rate="1:1", **kwargs):
platform = qmtech_5cefa2.Platform(with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTECH 5CEFA2" + (" + Daughterboard" if with_daughterboard else ""),
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -147,11 +146,9 @@ def main():
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output.")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
@ -163,7 +160,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
ident_version = args.no_ident_version,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
with_spi_flash = args.with_spi_flash,

5
litex_boards/targets/qmtech_ep4cex5.py
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@ -76,13 +76,12 @@ class BaseSoC(SoCCore):
def __init__(self, variant="ep4ce15", sys_clk_freq=int(50e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
ident_version=True, sdram_rate="1:1", **kwargs):
sdram_rate="1:1", **kwargs):
platform = qmtech_ep4cex5.Platform(variant=variant, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTECH EP4CE15" + (" + Daughterboard" if with_daughterboard else ""),
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -143,7 +142,6 @@ def main():
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output.")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
@ -160,7 +158,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
ident_version = args.no_ident_version,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
sdram_rate = args.sdram_rate,

5
litex_boards/targets/qmtech_xc7a35t.py
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@ -72,7 +72,7 @@ class BaseSoC(SoCCore):
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
ident_version=True, with_jtagbone=True, with_spi_flash=False, **kwargs):
with_jtagbone=True, with_spi_flash=False, **kwargs):
platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
# SoCCore ----------------------------------------------------------------------------------
@ -81,7 +81,6 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""),
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -155,7 +154,6 @@ def main():
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output.")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = parser.add_mutually_exclusive_group()
@ -174,7 +172,6 @@ def main():
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
ident_version = args.no_ident_version,
with_jtagbone = args.with_jtagbone,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,

5
litex_boards/targets/seeedstudio_spartan_edge_accelerator.py
View File

@ -61,7 +61,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), ident_version=True,
def __init__(self, sys_clk_freq=int(100e6),
with_led_chaser = True,
with_jtagbone = False,
with_video_terminal = True,
@ -73,7 +73,6 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Seeedstudio Spartan Edge Accelerator",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -110,7 +109,6 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Spartan Edge Accelerator")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Colorbars (HDMI).")
parser.add_argument("--with-neopixel", action="store_true", help="Enable onboard 2 Neopixels Leds.")
@ -121,7 +119,6 @@ def main():
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
ident_version = args.no_ident_version,
with_jtagbone = args.with_jtagbone,
with_video_terminal = args.with_video_terminal,
with_neopixel = args.with_neopixel,