targets/l2_cache_reverse: Now defaulting to False in LiteX, so setting it to False for correct Framebuffer operations is no longer required.

This commit is contained in:
Florent Kermarrec 2022-01-18 11:37:55 +01:00
parent 834125e978
commit d92a2b82fb
3 changed files with 10 additions and 13 deletions

View file

@ -112,11 +112,10 @@ class BaseSoC(SoCCore):
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False
phy = self.sdrphy,
module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Video ------------------------------------------------------------------------------------

View file

@ -86,10 +86,9 @@ class BaseSoC(SoCCore):
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = AS4C16M16(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False
phy = self.sdrphy,
module = AS4C16M16(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Video ------------------------------------------------------------------------------------

View file

@ -88,10 +88,9 @@ class BaseSoC(SoCCore):
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_reverse = False,
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Etherbone --------------------------------------------------------------------------------