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platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31)

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Florent Kermarrec 2020-03-10 14:57:39 +01:00
parent 95e1a05bf1
commit 75286f8a9b
1 changed files with 1 additions and 0 deletions
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litex_boards/platforms/zcu104.py
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@ -142,5 +142,6 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")