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targets/pcie: update timing_constraints (now provided by the .xci).

This commit is contained in:
Florent Kermarrec 2020-09-24 09:50:55 +02:00
parent c6610b4a3f
commit 77ba49f2bb
7 changed files with 0 additions and 7 deletions
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1
litex_boards/targets/acorn_cle_215.py
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@ -111,7 +111,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
self.comb += platform.request("pcie_clkreq_n").eq(0)

1
litex_boards/targets/aller.py
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@ -94,7 +94,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")

1
litex_boards/targets/alveo_u250.py
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@ -100,7 +100,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
#self.pcie_phy.add_timing_constraints(platform) # FIXME
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")

1
litex_boards/targets/fk33.py
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@ -58,7 +58,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
#self.pcie_phy.add_timing_constraints(platform) # FIXME
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")

1
litex_boards/targets/nereid.py
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@ -91,7 +91,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")

1
litex_boards/targets/tagus.py
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@ -94,7 +94,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 64,
bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")

1
litex_boards/targets/xcu1525.py
View File

@ -98,7 +98,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
#self.pcie_phy.add_timing_constraints(platform) # FIXME
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")