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targets: switch from shadow_base to io_regions

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This commit is contained in:
Florent Kermarrec 2019-10-09 11:09:59 +02:00
parent 19e2a12266
commit 785909ac5f
12 changed files with 24 additions and 24 deletions
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4
litex_boards/community/targets/ac701.py
View file

@ -72,7 +72,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -123,7 +123,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/arty.py
View file

@ -72,7 +72,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -85,7 +85,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/genesys2.py
View file

@ -65,7 +65,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -78,7 +78,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/kc705.py
View file

@ -67,7 +67,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -80,7 +80,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/kcu105.py
View file

@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -117,7 +117,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/nexys4ddr.py
View file

@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/nexys_video.py
View file

@ -70,7 +70,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -83,7 +83,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/simple.py
View file

@ -31,7 +31,7 @@ class BaseSoC(SoCCore):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -44,7 +44,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/official/targets/versa_ecp5.py
View file

@ -102,7 +102,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -116,7 +116,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/partner/targets/c10lprefkit.py
View file

@ -110,7 +110,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -123,7 +123,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/partner/targets/netv2.py
View file

@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex_boards/partner/targets/trellisboard.py
View file

@ -104,7 +104,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -118,7 +118,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")