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targets: add indentifier on all targets.

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This commit is contained in:
Florent Kermarrec 2020-06-30 18:11:04 +02:00
parent fc22e28fe9
commit 7a48a61605
39 changed files with 164 additions and 48 deletions
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5
litex_boards/targets/ac701.py
View file

@ -52,7 +52,10 @@ class BaseSoC(SoCCore):
platform = ac701.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on AC701",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/alveo_u250.py
View file

@ -56,7 +56,10 @@ class BaseSoC(SoCCore):
platform = alveo_u250.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Alveo U250",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/arty.py
View file

@ -56,7 +56,10 @@ class BaseSoC(SoCCore):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/arty_s7.py
View file

@ -51,7 +51,10 @@ class BaseSoC(SoCCore):
platform = arty_s7.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty S7",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/c10lprefkit.py
View file

@ -59,7 +59,10 @@ class BaseSoC(SoCCore):
platform = c10lprefkit.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on C10 LP RefKit",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/camlink_4k.py
View file

@ -74,7 +74,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = int(81e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Cam Link 4K",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

7
litex_boards/targets/colorlight_5a_75x.py
View file

@ -107,7 +107,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Colorlight " + board.upper(),
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
@ -141,7 +144,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75B")
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

7
litex_boards/targets/de0nano.py
View file

@ -50,7 +50,10 @@ class BaseSoC(SoCCore):
platform = de0nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DE0-Nano",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -77,7 +80,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano")
parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)

7
litex_boards/targets/de10lite.py
View file

@ -55,7 +55,10 @@ class BaseSoC(SoCCore):
platform = de10lite.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DE10-Lite",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -95,7 +98,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite")
parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)

7
litex_boards/targets/de10nano.py
View file

@ -55,7 +55,10 @@ class BaseSoC(SoCCore):
platform = de10nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DE10-Nano",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram)
@ -95,7 +98,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano")
parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)

5
litex_boards/targets/de1soc.py
View file

@ -49,7 +49,10 @@ class BaseSoC(SoCCore):
platform = de1soc.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DE1-SoC",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/de2_115.py
View file

@ -49,7 +49,10 @@ class BaseSoC(SoCCore):
platform = de2_115.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DE2-115",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/ecp5_evn.py
View file

@ -46,7 +46,10 @@ class BaseSoC(SoCCore):
platform = ecp5_evn.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ECP5 Evaluation Board",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg = _CRG(platform, sys_clk_freq, x5_clk_freq)

5
litex_boards/targets/ecpix5.py
View file

@ -77,7 +77,10 @@ class BaseSoC(SoCCore):
platform = ecpix5.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ECPIX-5",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/forest_kitten_33.py
View file

@ -34,7 +34,10 @@ class BaseSoC(SoCCore):
platform = forest_kitten_33.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Forest Kitten 33",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/genesys2.py
View file

@ -47,7 +47,10 @@ class BaseSoC(SoCCore):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Genesys2",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/hadbadge.py
View file

@ -57,7 +57,10 @@ class BaseSoC(SoCCore):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Hackaday Badge",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/icebreaker.py
View file

@ -80,7 +80,10 @@ class BaseSoC(SoCCore):
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on iCEBreaker",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/kc705.py
View file

@ -49,7 +49,10 @@ class BaseSoC(SoCCore):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on KC705",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/kcu105.py
View file

@ -56,7 +56,10 @@ class BaseSoC(SoCCore):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on KCU105",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/kx2.py
View file

@ -46,7 +46,10 @@ class BaseSoC(SoCCore):
platform = kx2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on KX2",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/linsn_rv901t.py
View file

@ -51,7 +51,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = int(75e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Linsn RV901T",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/logicbone.py
View file

@ -104,7 +104,10 @@ class BaseSoC(SoCCore):
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Logicbone",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"

7
litex_boards/targets/mercury_xu5.py
View file

@ -55,7 +55,10 @@ class BaseSoC(SoCCore):
platform = mercury_xu5.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Mercury XU5",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -87,7 +90,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Enclustra's Mercury XU5")
parser = argparse.ArgumentParser(description="LiteX SoC on Mercury XU5")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)

5
litex_boards/targets/mimas_a7.py
View file

@ -51,7 +51,10 @@ class BaseSoC(SoCCore):
platform = mimas_a7.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Mimas A7",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/minispartan6.py
View file

@ -49,7 +49,10 @@ class BaseSoC(SoCCore):
platform = minispartan6.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on MiniSpartan6",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/netv2.py
View file

@ -52,7 +52,10 @@ class BaseSoC(SoCCore):
platform = netv2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on NeTV2",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/nexys4ddr.py
View file

@ -53,7 +53,10 @@ class BaseSoC(SoCCore):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Nexys4DDR",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/nexys_video.py
View file

@ -53,7 +53,10 @@ class BaseSoC(SoCCore):
platform = nexys_video.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Nexys Video",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

6
litex_boards/targets/orangecrab.py
View file

@ -34,7 +34,6 @@ class _CRG(Module):
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
@ -102,7 +101,10 @@ class BaseSoC(SoCCore):
platform.add_extension(orangecrab.feather_serial)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on OrangeCrab",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"

5
litex_boards/targets/pano_logic_g2.py
View file

@ -45,7 +45,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Pano Logic G2",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_ethernet or with_etherbone)

7
litex_boards/targets/pipistrello.py
View file

@ -154,8 +154,11 @@ class BaseSoC(SoCCore):
sys_clk_freq = (83 + Fraction(1, 3))*1000*1000
platform = pipistrello.Platform()
# SoCCore -----------------------------------------------------------------_----------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Pipistrello",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/simple.py
View file

@ -24,7 +24,10 @@ class BaseSoC(SoCCore):
sys_clk_freq = int(1e9/platform.default_clk_period)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX Simple SoC",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

7
litex_boards/targets/trellisboard.py
View file

@ -88,8 +88,11 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore -----------------------------------------------------------------_----------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Trellis Board",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/ulx3s.py
View file

@ -74,7 +74,10 @@ class BaseSoC(SoCCore):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ULX3S",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"

7
litex_boards/targets/vc707.py
View file

@ -46,8 +46,11 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = vc707.Platform()
# SoCCore ------------------------------------------------------------------_---------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on VC707",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/vcu118.py
View file

@ -55,7 +55,10 @@ class BaseSoC(SoCCore):
platform = vcu118.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on VCU118",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/versa_ecp5.py
View file

@ -83,7 +83,10 @@ class BaseSoC(SoCCore):
kwargs["integrated_rom_size"] = 0xb000 if with_ethernet else 0x9000
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Versa ECP5",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

5
litex_boards/targets/zcu104.py
View file

@ -55,7 +55,10 @@ class BaseSoC(SoCCore):
platform = zcu104.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ZCU104",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)