xcu1525: add initial DDR4 support in C0 (untested).
This commit is contained in:
Florent Kermarrec
parent
5a62a07b45
commit
7b6b71d4e3
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@ -35,6 +35,49 @@ _io = [
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Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8")),
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Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")),
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),
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# ddram
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("ddram", 0,
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Subsignal("a", Pins(
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"AT36 AV36 AV37 AW35 AW36 AY36 AY35 BA40",
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"BA37 BB37 AR35 BA39 BB40 AN36"),
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IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("BB39"), IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AT35 AT34"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BC37 BC39"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("AP36"), IOStandard("SSTL12_DCI")),
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Subsignal("cke", Pins("BC38"), IOStandard("SSTL12_DCI")),
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Subsignal("clk_n", Pins("AW38"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_p", Pins("AV38"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cs_n", Pins("AR33"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AM32 AP31 AL29 AT30 AU30 AY28 BE36 BE32"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"AW28 AW29 BA28 BA27 BB29 BA29 BC27 BB27",
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"BE28 BF28 BE30 BD30 BF27 BE27 BF30 BF29",
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"BB31 BB32 AY32 AY33 BC32 BC33 BB34 BC34",
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"AV31 AV32 AV34 AW34 AW31 AY31 BA35 BA34",
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"AL30 AM30 AU32 AT32 AN31 AN32 AR32 AR31",
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"AP29 AP28 AN27 AM27 AN29 AM29 AR27 AR28",
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"AT28 AV27 AU27 AT27 AV29 AY30 AW30 AV28",
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"BD34 BD33 BE33 BD35 BF32 BF33 BF34 BF35"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("BB30 BC26 BD29 BE26 BB36 BD31 AW33 BA33"),
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("BA30 BB26 BD28 BD26 BB35 BC31 AV33 BA32"),
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AR36"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("AU31"), IOStandard("LVCMOS12")),
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Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")),
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Misc("SLEW=FAST")
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),
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]
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_connectors = []
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@ -58,3 +101,6 @@ class Platform(XilinxPlatform):
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
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# Reduce programming time
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self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 61]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 62]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 63]")
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@ -16,6 +16,9 @@ from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT40A512M8
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from litedram.phy import usddrphy
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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@ -27,12 +30,27 @@ from litepcie.software import generate_litepcie_software
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk500 = ClockDomain()
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# # #
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self.submodules.pll = pll = USPMMCM(speedgrade=-2)
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pll.register_clkin(platform.request("clk300"), 300e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_clk500, ~pll.locked),
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]
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self.submodules.idelayctrl = USPIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -49,6 +67,24 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 500e6,
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cmd_latency = 1)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT40A512M8(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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# PHY
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