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litex-boards
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targets/pcie: Cleanup.

This commit is contained in:
Florent Kermarrec 2021-03-25 17:47:06 +01:00
parent 333fb362ca
commit 7d130d6981
4 changed files with 3 additions and 4 deletions
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2
litex_boards/targets/kosagi_netv2.py
View File

@ -101,7 +101,7 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
bar0_size = 0x20000) bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1, max_pending_requests=2) self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(

2
litex_boards/targets/numato_tagus.py
View File

@ -89,7 +89,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 128, data_width = 64,
bar0_size = 0x20000) bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1) self.add_pcie(phy=self.pcie_phy, ndmas=1)

2
litex_boards/targets/rhsresearchllc_litefury.py
View File

@ -88,7 +88,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 64, data_width = 128,
bar0_size = 0x20000) bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1) self.add_pcie(phy=self.pcie_phy, ndmas=1)

1
litex_boards/targets/sqrl_fk33.py
View File

@ -62,7 +62,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
bar0_size = 0x20000) bar0_size = 0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
# Endpoint # Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)