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qmtech altera boards: sdram io properties for more speed

This commit is contained in:
Hans Baier 2024-03-30 20:24:01 +07:00
parent 2505aeb9b4
commit 7d89aa0fe9
7 changed files with 32 additions and 7 deletions
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7
litex_boards/platforms/qmtech_10cl006.py
View File

@ -42,8 +42,13 @@ _io = [
Subsignal("we_n", Pins("P6")),
Subsignal("dq", Pins(
"K5 L3 L4 K6 N3 M6 P3 N5",
"N2 N1 L1 L2 K1 K2 J1 J2")),
"N2 N1 L1 L2 K1 K2 J1 J2"),
Misc("FAST_OUTPUT_ENABLE_REGISTER ON"),
Misc("FAST_INPUT_REGISTER ON")),
Subsignal("dm", Pins("N6 P1")),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
Misc("FAST_OUTPUT_REGISTER ON"),
Misc("ALLOW_SYNCH_CTRL_USAGE OFF"),
IOStandard("3.3-V LVTTL")
),
]

7
litex_boards/platforms/qmtech_5cefa2.py
View File

@ -42,8 +42,13 @@ _io = [
Subsignal("we_n", Pins("W9")),
Subsignal("dq", Pins(
"AA12 Y11 AA10 AB10 Y10 AA9 AB8 AA8",
" U10 T10 U11 R12 U12 P12 R10 R11")),
" U10 T10 U11 R12 U12 P12 R10 R11"),
Misc("FAST_OUTPUT_ENABLE_REGISTER ON"),
Misc("FAST_INPUT_REGISTER ON")),
Subsignal("dm", Pins("AB7 V10")),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
Misc("FAST_OUTPUT_REGISTER ON"),
Misc("ALLOW_SYNCH_CTRL_USAGE OFF"),
IOStandard("3.3-V LVTTL")
),
]

7
litex_boards/platforms/qmtech_5cefa5.py
View File

@ -44,8 +44,13 @@ _io = [
Subsignal("we_n", Pins("U20")),
Subsignal("dq", Pins(
"AA22 AB22 Y22 Y21 W22 W21 V21 U22 M21 M22 T22 R21 R22 P22 N20 N21 ",
"K22 K21 J22 J21 H21 G22 G21 F22 E22 E20 D22 D21 C21 B22 A22 B21")),
"K22 K21 J22 J21 H21 G22 G21 F22 E22 E20 D22 D21 C21 B22 A22 B21"),
Misc("FAST_OUTPUT_ENABLE_REGISTER ON"),
Misc("FAST_INPUT_REGISTER ON")),
Subsignal("dm", Pins("U21 L22 K20 E21")),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
Misc("FAST_OUTPUT_REGISTER ON"),
Misc("ALLOW_SYNCH_CTRL_USAGE OFF"),
IOStandard("3.3-V LVCMOS")
),
]

7
litex_boards/platforms/qmtech_ep4cex5.py
View File

@ -43,8 +43,13 @@ _io = [
Subsignal("we_n", Pins("AB4")),
Subsignal("dq", Pins(
"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
"Y7 W8 Y8 V9 V10 Y10 W10 V11"),
Misc("FAST_OUTPUT_ENABLE_REGISTER ON"),
Misc("FAST_INPUT_REGISTER ON")),
Subsignal("dm", Pins("AA5 W7")),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
Misc("FAST_OUTPUT_REGISTER ON"),
Misc("ALLOW_SYNCH_CTRL_USAGE OFF"),
IOStandard("3.3-V LVTTL")
),
]

7
litex_boards/platforms/qmtech_ep4cgx150.py
View File

@ -43,8 +43,13 @@ _io = [
Subsignal("we_n", Pins("G25")),
Subsignal("dq", Pins(
"B25 B26 C25 C26 D25 D26 E25 E26",
"H23 G24 G22 F24 F23 E24 D24 C24")),
"H23 G24 G22 F24 F23 E24 D24 C24"),
Misc("FAST_OUTPUT_ENABLE_REGISTER ON"),
Misc("FAST_INPUT_REGISTER ON")),
Subsignal("dm", Pins("F26 H24")),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
Misc("FAST_OUTPUT_REGISTER ON"),
Misc("ALLOW_SYNCH_CTRL_USAGE OFF"),
IOStandard("3.3-V LVTTL")
),
]

2
litex_boards/targets/qmtech_5cefa5.py
View File

@ -75,7 +75,7 @@ class _CRG(LiteXModule):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=80e6, with_daughterboard=False,
def __init__(self, sys_clk_freq=95e6, with_daughterboard=False,
with_ethernet = False,
with_etherbone = False,
eth_ip = "192.168.1.50",

2
litex_boards/targets/qmtech_ep4cgx150.py
View File

@ -136,7 +136,7 @@ class BaseSoC(SoCCore):
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=qmtech_ep4cgx150.Platform, description="LiteX SoC on QMTECH EP4CE15.")
parser.add_target_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.")
parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
parser.add_target_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
ethopts = parser.target_group.add_mutually_exclusive_group()