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targets/kc705: switch SATA to gen2.

This commit is contained in:
Florent Kermarrec 2020-10-28 19:09:06 +01:00
parent 931f6667ac
commit 7da8628fba
1 changed files with 3 additions and 3 deletions
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6
litex_boards/targets/kc705.py
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@ -117,7 +117,7 @@ class BaseSoC(SoCCore):
self.submodules.sata_phy = LiteSATAPHY(platform.device, self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk = sata_refclk, refclk = sata_refclk,
pads = platform.request("sfp"), pads = platform.request("sfp"),
gen = "gen1", gen = "gen2",
clk_freq = sys_clk_freq, clk_freq = sys_clk_freq,
data_width = 16) data_width = 16)
@ -137,8 +137,8 @@ class BaseSoC(SoCCore):
self.add_csr("sata_block2mem") self.add_csr("sata_block2mem")
# Timing constraints # Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6) platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6) platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
self.sata_phy.crg.cd_sata_tx.clk, self.sata_phy.crg.cd_sata_tx.clk,