targets/kc705: switch SATA to gen2.
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@ -117,7 +117,7 @@ class BaseSoC(SoCCore):
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self.submodules.sata_phy = LiteSATAPHY(platform.device,
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refclk = sata_refclk,
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pads = platform.request("sfp"),
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gen = "gen1",
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gen = "gen2",
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clk_freq = sys_clk_freq,
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data_width = 16)
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@ -137,8 +137,8 @@ class BaseSoC(SoCCore):
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self.add_csr("sata_block2mem")
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# Timing constraints
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6)
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6)
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6)
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/150e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.sata_phy.crg.cd_sata_tx.clk,
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