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Merge pull request #469 from hansfbaier/hpcstore-rename 

HPC FPGA Store on AliExpress renamed itself to SITLINV
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enjoy-digital 2023-01-17 11:20:19 +01:00 committed by GitHub
parent 55fcb4cd47 c0773ed9b9
commit 801008f5ad
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2 changed files with 6 additions and 6 deletions
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2
litex_boards/platforms/hpcstore_xc7k420t.py → litex_boards/platforms/sitlinv_xc7k420t.py
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@ -8,7 +8,7 @@ from litex.build.generic_platform import *
from litex.build.xilinx import Xilinx7SeriesPlatform
from litex.build.openocd import OpenOCD
# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store"
# Board support for this chinese Kintex 420T board by "SITLINV FPGA Board Store"
# https://www.aliexpress.com/item/1005001631827738.html
# IOs ----------------------------------------------------------------------------------------------

10
litex_boards/targets/hpcstore_xc7k420t.py → litex_boards/targets/sitlinv_xc7k420t.py
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@ -10,7 +10,7 @@
# Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store"
# Board support for this chinese Kintex 420T board by "SITLINV FPGA Board Store"
# https://www.aliexpress.com/item/1005001631827738.html
import os
@ -19,7 +19,7 @@ from migen import *
from litex.gen import LiteXModule
from litex_boards.platforms import hpcstore_xc7k420t
from litex_boards.platforms import sitlinv_xc7k420t
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
@ -71,13 +71,13 @@ class BaseSoC(SoCCore):
with_pcie = False,
with_sata = False,
**kwargs):
platform = hpcstore_xc7k420t.Platform(io_voltage)
platform = sitlinv_xc7k420t.Platform(io_voltage)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on HPC Store XC7K420T", **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on SITLINV XC7K420T", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
@ -139,7 +139,7 @@ class BaseSoC(SoCCore):
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=hpcstore_xc7k420t.Platform, description="LiteX SoC on AliExpress HPC Store XC7K420T")
parser = LiteXArgumentParser(platform=sitlinv_xc7k420t.Platform, description="LiteX SoC on AliExpress SITLINV FPGA Store XC7K420T")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--io-voltage", default="3.3V", help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'.")
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")