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hadbadge: remove speed_grade workaround, now passed to trellis from device.

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This commit is contained in:
Florent Kermarrec 2020-01-08 19:44:35 +01:00
parent 1f300bb03e
commit 82601ff700
2 changed files with 1 additions and 2 deletions
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2
litex_boards/partner/platforms/hadbadge.py
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@ -208,7 +208,7 @@ class Platform(LatticePlatform):
default_clk_period = 1e9/8e6 default_clk_period = 1e9/8e6
def __init__(self, toolchain="trellis", **kwargs): def __init__(self, toolchain="trellis", **kwargs):
LatticePlatform.__init__(self, "LFE5U-45F-CABGA381", io=_io, connectors=_connectors, LatticePlatform.__init__(self, "LFE5U-45F-8CABGA381", io=_io, connectors=_connectors,
toolchain=toolchain, **kwargs) toolchain=toolchain, **kwargs)
def create_programmer(self): def create_programmer(self):

1
litex_boards/partner/targets/hadbadge.py
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@ -54,7 +54,6 @@ class _CRG(Module):
class BaseSoC(SoCSDRAM): class BaseSoC(SoCSDRAM):
def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs): def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
platform = hadbadge.Platform(toolchain=toolchain) platform = hadbadge.Platform(toolchain=toolchain)
platform.toolchain.build_template[1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5 # FIXME
# SoCSDRAM --------------------------------------------------------------------------------- # SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,