Merge pull request #321 from r4d10n/master
Support for Digilent Pynq Z1
This commit is contained in:
enjoy-digital
GitHub
commit
830757502f
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Rakesh Peter <rakesh@stanproc.in>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("sysclk", 0, Pins("H16"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("L15"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("G17"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("N15"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("G14"), IOStandard("LVCMOS33")),
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("user_led", 8, Pins("L14"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("M15"), IOStandard("LVCMOS33")),
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# Switches
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("user_sw", 0, Pins("M20"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("M19"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("D19"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("D20"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")),
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#Serial
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("serial", 0,
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Subsignal("tx", Pins("pmoda:0")),
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Subsignal("rx", Pins("pmoda:1")),
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IOStandard("LVCMOS33")
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),
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# Audio
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("aud_pwm", 0, Pins("R18"), IOStandard("LVCMOS33")),
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("aud_sd", 0, Pins("T17"), IOStandard("LVCMOS33")),
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("m_clk", 0, Pins("F17"), IOStandard("LVCMOS33")),
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("m_data", 0, Pins("G18"), IOStandard("LVCMOS33")),
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# Chipkit Single Ended Analog Input
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("ck_an_n", 0, Pins("D18"), IOStandard("LVCMOS33")),
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("ck_an_p", 0, Pins("E17"), IOStandard("LVCMOS33")),
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("ck_an_n", 1, Pins("E19"), IOStandard("LVCMOS33")),
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("ck_an_p", 1, Pins("E18"), IOStandard("LVCMOS33")),
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("ck_an_n", 2, Pins("J14"), IOStandard("LVCMOS33")),
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("ck_an_p", 2, Pins("K14"), IOStandard("LVCMOS33")),
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("ck_an_n", 3, Pins("J16"), IOStandard("LVCMOS33")),
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("ck_an_p", 3, Pins("K16"), IOStandard("LVCMOS33")),
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("ck_an_n", 4, Pins("H20"), IOStandard("LVCMOS33")),
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("ck_an_p", 4, Pins("J20"), IOStandard("LVCMOS33")),
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("ck_an_n", 5, Pins("G20"), IOStandard("LVCMOS33")),
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("ck_an_p", 5, Pins("G19"), IOStandard("LVCMOS33")),
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# Chipkit SPI
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("ck_miso", 0, Pins("W15"), IOStandard("LVCMOS33")),
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("ck_mosi", 0, Pins("T12"), IOStandard("LVCMOS33")),
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("ck_sck", 0, Pins("H15"), IOStandard("LVCMOS33")),
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("ck_ss", 0, Pins("F16"), IOStandard("LVCMOS33")),
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# Chipkit I2C
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("ck_scl", 0, Pins("P16"), IOStandard("LVCMOS33")),
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("ck_sda", 0, Pins("P15"), IOStandard("LVCMOS33")),
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# Crypto SDA
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("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33"))
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]
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_ps7_io = [
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# PS7
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("ps7_clk", 0, Pins("E7")),
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("ps7_porb", 0, Pins("C7")),
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("ps7_srstb", 0, Pins("B10")),
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("ps7_mio", 0, Pins(
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"E6 A7 B8 D6 B7 A6 A5 D8",
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"D5 B5 E9 C6 D9 E8 C5 C8",
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"A19 E14 B18 D10 A17 F14 B17 D11",
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"A16 F15 A15 D13 C16 C13 C15 E16",
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"A14 D15 A12 F12 A11 A10 E13 C18"
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"D14 C17 E12 A9 F13 B15 D16 B14"
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"B12 C12 B13 B9 C10 C11")),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(
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"N2 K2 M3 K3 M4 L1 L4 K4",
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"K1 J4 F5 G4 E4 D4 F4")),
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Subsignal("ba", Pins("L5 R4 J5")),
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Subsignal("cas_n", Pins("P5")),
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Subsignal("cke", Pins("N3")),
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Subsignal("ck_n", Pins("M2")),
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Subsignal("ck_p", Pins("L2")),
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Subsignal("cs_n", Pins("N1")),
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Subsignal("dm", Pins("A1 F1 T1 Y1")),
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Subsignal("dq", Pins(
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" C3 B3 A2 A4 D3 D1 C1 E1",
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" E2 E3 G3 H3 J3 H2 H1 J1",
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" P1 P3 R3 R1 T4 U4 U2 U3",
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" V1 Y3 W1 Y4 Y2 W3 V2 V3"),
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),
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Subsignal("dqs_n", Pins("B2 F2 T2 W4")),
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Subsignal("dqs_p", Pins("C2 G2 R2 W5")),
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Subsignal("reset_n", Pins("B4")),
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Subsignal("odt", Pins("N5")),
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Subsignal("ras_n", Pins("P4")),
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Subsignal("vrn", Pins("G5")),
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Subsignal("vrp", Pins("H5")),
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Subsignal("we_n", Pins("M5"))
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),
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]
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_hdmi_rx_io = [
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# HDMI Rx
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("hdmi_rx", 0,
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Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("N18"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")),
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Subsignal("hpd", Pins("T19"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")),
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),
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]
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_hdmi_tx_io = [
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# HDMI Tx
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("hdmi_tx", 0,
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Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")),
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Subsignal("hpdn", Pins("R19"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmoda", "Y18 Y19 Y16 Y17 U18 U19 W18 W19"), # XADC
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("pmodb", "W14 Y14 T11 T10 V16 W16 V12 W13"),
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("ck_io", "T14 U12 U13 V13 V15 T15 R16 U17 V17 V18 T16 R17 P18 N17 Y11 Y12 W11 V11 T5 U10 B20 C20 F20 F19 A20 B19 U5 V5 V6 U7 V7 U8 V8 V10 W10 W6 Y6 Y7 W8 Y8 W9 Y9 Y13")
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "sysclk"
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default_clk_period = 1e9/125e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, _connectors, toolchain="vivado")
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self.add_extension(_ps7_io)
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self.add_extension(_hdmi_rx_io)
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self.add_extension(_hdmi_tx_io)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("sysclk", loose=True), 1e9/125e6)
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@ -0,0 +1,130 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Rakesh Peter <rakesh@stanproc.in>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import pynq_z1
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, toolchain, use_ps7_clk=False, with_video_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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# # #
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# Clk
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clk125 = platform.request("sysclk")
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# PLL
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if use_ps7_clk:
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assert sys_clk_freq == 125e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk125, 125e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# Video PLL.
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if with_video_pll:
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=-1)
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video_pll.reset.eq(self.rst)
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video_pll.register_clkin(clk125, 125e6)
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video_pll.create_clkout(self.cd_hdmi, 40e6)
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video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_led_chaser=True,
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with_video_terminal=False, with_video_framebuffer=False, **kwargs):
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platform = pynq_z1.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on PYNQ Z1",
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ident_version = True,
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
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os.system("wget https://github.com/litex-hub/litex-boards/files/4967144/zybo_z7_ps7.txt")
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os.makedirs("xci", exist_ok=True)
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os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
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self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = 0x43c00000)
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self.add_wb_master(wb_gp0)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_terminal)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_tx"), clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on PYNQ Z1")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1)
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if __name__ == "__main__":
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main()
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