targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.
This commit is contained in:
Florent Kermarrec
parent
9f11bfb0d1
commit
843e724e3d
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@ -103,6 +103,16 @@ _io = [
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Subsignal("tx_n", Pins("C10"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")),
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Subsignal("clk_p", Pins("F11")),
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Subsignal("clk_n", Pins("E11")),
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Subsignal("rx_p", Pins("D12 B13 D14 B11")),
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Subsignal("rx_n", Pins("C12 A13 C14 A11")),
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Subsignal("tx_p", Pins("D10 B9 D8 B7")),
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Subsignal("tx_n", Pins("C10 A9 C8 A7"))
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),
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# GTP RefClk
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("gtp_refclk", 0,
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Subsignal("p", Pins("AA13")),
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@ -4,7 +4,7 @@
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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@ -28,6 +28,9 @@ from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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@ -53,7 +56,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, ethernet_phy="rgmii", **kwargs):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, ethernet_phy="rgmii", with_pcie=False, **kwargs):
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platform = ac701.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -121,6 +124,14 @@ class BaseSoC(SoCCore):
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self.add_ethernet(phy=self.ethphy)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_csr("pcie_phy")
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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@ -136,12 +147,21 @@ def main():
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY: rgmii (default) or 1000basex")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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args = parser.parse_args()
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soc = BaseSoC(with_ethernet=args.with_ethernet, ethernet_phy=args.ethernet_phy, **soc_sdram_argdict(args))
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soc = BaseSoC(
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with_ethernet = args.with_ethernet,
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ethernet_phy = args.ethernet_phy,
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with_pcie = args.with_pcie,
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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@ -43,9 +43,6 @@ from litedram.modules import MT41K512M16
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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@ -108,50 +105,11 @@ class BaseSoC(SoCCore):
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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assert self.csr_data_width == 32
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# PHY
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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self.comb += platform.request("pcie_clkreq_n").eq(0)
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# Endpoint
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
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# Wishbone bridge
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self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
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base_address = self.mem_map["csr"])
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self.add_wb_master(self.pcie_bridge.wishbone)
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# DMA0
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self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma0")
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# DMA1
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self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma1")
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self.add_constant("DMA_CHANNELS", 2)
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# MSI
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self.submodules.pcie_msi = LitePCIeMSI()
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self.add_csr("pcie_msi")
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.interrupts = {
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"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
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"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
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"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
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"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
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}
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for i, (k, v) in enumerate(sorted(self.interrupts.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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@ -164,24 +122,22 @@ class BaseSoC(SoCCore):
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--flash", action="store_true", help="Flash bitstream")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
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soc = BaseSoC(with_pcie = args.with_pcie, **soc_sdram_argdict(args))
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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@ -4,7 +4,7 @@
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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@ -27,9 +27,6 @@ from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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@ -91,41 +88,11 @@ class BaseSoC(SoCCore):
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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assert self.csr_data_width == 32
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# PHY
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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# Endpoint
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
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# Wishbone bridge
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self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
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base_address = self.mem_map["csr"])
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self.add_wb_master(self.pcie_bridge.wishbone)
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# DMA0
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self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma0")
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self.add_constant("DMA_CHANNELS", 1)
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# MSI
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self.submodules.pcie_msi = LitePCIeMSI()
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self.add_csr("pcie_msi")
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.interrupts = {
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"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
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"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
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}
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for i, (k, v) in enumerate(sorted(self.interrupts.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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@ -25,9 +25,6 @@ from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy import usddrphy
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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@ -97,41 +94,11 @@ class BaseSoC(SoCCore):
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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assert self.csr_data_width == 32
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# PHY
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self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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# Endpoint
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
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# Wishbone bridge
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self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
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base_address = self.mem_map["csr"])
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self.add_wb_master(self.pcie_bridge.wishbone)
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# DMA0
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self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma0")
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self.add_constant("DMA_CHANNELS", 1)
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# MSI
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self.submodules.pcie_msi = LitePCIeMSI()
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self.add_csr("pcie_msi")
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.interrupts = {
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"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
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"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
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}
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for i, (k, v) in enumerate(sorted(self.interrupts.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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@ -4,7 +4,7 @@
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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@ -26,6 +26,9 @@ from litedram.phy import s7ddrphy
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from liteeth.phy import LiteEthPHY
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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@ -49,7 +52,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_sata=False, **kwargs):
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def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_pcie=False, with_sata=False, **kwargs):
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platform = kc705.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -87,6 +90,14 @@ class BaseSoC(SoCCore):
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_csr("pcie_phy")
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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@ -135,15 +146,25 @@ def main():
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA)")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args))
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soc = BaseSoC(
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with_ethernet = args.with_ethernet,
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with_pcie = args.with_pcie,
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with_sata = args.with_sata,
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**soc_sdram_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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@ -3,7 +3,7 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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@ -25,6 +25,9 @@ from litedram.phy import usddrphy
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from liteeth.phy.ku_1000basex import KU_1000BASEX
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from litepcie.phy.uspciephy import USPCIEPHY
|
||||
from litepcie.software import generate_litepcie_software
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class _CRG(Module):
|
||||
|
|
@ -59,7 +62,7 @@ class _CRG(Module):
|
|||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, **kwargs):
|
||||
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, with_pcie=False, **kwargs):
|
||||
platform = kcu105.Platform()
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
|
|
@ -101,6 +104,14 @@ class BaseSoC(SoCCore):
|
|||
if with_etherbone:
|
||||
self.add_etherbone(phy=self.ethphy)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
self.add_csr("pcie_phy")
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
self.submodules.leds = LedChaser(
|
||||
pads = platform.request_all("user_led"),
|
||||
|
|
@ -113,18 +124,27 @@ def main():
|
|||
parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
|
||||
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
assert not (args.with_ethernet and args.with_etherbone)
|
||||
soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
|
||||
**soc_sdram_argdict(args))
|
||||
soc = BaseSoC(
|
||||
with_ethernet = args.with_ethernet,
|
||||
with_etherbone = args.with_etherbone,
|
||||
with_pcie = args.with_pcie,
|
||||
**soc_sdram_argdict(args)
|
||||
)
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
if args.driver:
|
||||
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
|
||||
# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
import os
|
||||
|
|
@ -26,9 +26,6 @@ from litedram.modules import MT8KTF51264
|
|||
from litedram.phy import s7ddrphy
|
||||
|
||||
from litepcie.phy.s7pciephy import S7PCIEPHY
|
||||
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
|
||||
from litepcie.frontend.dma import LitePCIeDMA
|
||||
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
|
||||
from litepcie.software import generate_litepcie_software
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
|
@ -86,52 +83,23 @@ class BaseSoC(SoCCore):
|
|||
l2_cache_reverse = True
|
||||
)
|
||||
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
assert self.csr_data_width == 32
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
|
||||
self.add_csr("pcie_phy")
|
||||
|
||||
# Endpoint
|
||||
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
|
||||
|
||||
# Wishbone bridge
|
||||
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
|
||||
base_address = self.mem_map["csr"])
|
||||
self.add_wb_master(self.pcie_bridge.wishbone)
|
||||
|
||||
# DMA0
|
||||
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 1)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
self.add_csr("pcie_msi")
|
||||
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
|
||||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
self.add_constant(k + "_INTERRUPT", i)
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on Nereid")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
|
|
|||
|
|
@ -28,9 +28,6 @@ from litedram.phy import s7ddrphy
|
|||
from liteeth.phy.rmii import LiteEthPHYRMII
|
||||
|
||||
from litepcie.phy.s7pciephy import S7PCIEPHY
|
||||
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
|
||||
from litepcie.frontend.dma import LitePCIeDMA
|
||||
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
|
||||
from litepcie.software import generate_litepcie_software
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
|
@ -103,41 +100,11 @@ class BaseSoC(SoCCore):
|
|||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
assert self.csr_data_width == 32
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
|
||||
self.add_csr("pcie_phy")
|
||||
|
||||
# Endpoint
|
||||
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
|
||||
|
||||
# Wishbone bridge
|
||||
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
|
||||
base_address = self.mem_map["csr"])
|
||||
self.add_wb_master(self.pcie_bridge.wishbone)
|
||||
|
||||
# DMA0
|
||||
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 1)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
self.add_csr("pcie_msi")
|
||||
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
|
||||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
self.add_constant(k + "_INTERRUPT", i)
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
self.submodules.leds = LedChaser(
|
||||
|
|
@ -161,7 +128,11 @@ def main():
|
|||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(with_ethernet=args.with_ethernet, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
|
||||
soc = BaseSoC(
|
||||
with_ethernet = args.with_ethernet,
|
||||
with_pcie = args.with_pcie,
|
||||
**soc_sdram_argdict(args)
|
||||
)
|
||||
assert not (args.with_spi_sdcard and args.with_sdcard)
|
||||
if args.with_spi_sdcard:
|
||||
soc.add_spi_sdcard()
|
||||
|
|
@ -170,7 +141,6 @@ def main():
|
|||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
|
||||
if args.driver:
|
||||
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
|
||||
# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
import os
|
||||
|
|
@ -26,10 +26,8 @@ from litex.soc.cores.led import LedChaser
|
|||
from litedram.modules import MT41J128M16
|
||||
from litedram.phy import s7ddrphy
|
||||
|
||||
|
||||
from litepcie.phy.s7pciephy import S7PCIEPHY
|
||||
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
|
||||
from litepcie.frontend.dma import LitePCIeDMA
|
||||
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
|
||||
from litepcie.software import generate_litepcie_software
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
|
@ -91,41 +89,11 @@ class BaseSoC(SoCCore):
|
|||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
assert self.csr_data_width == 32
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
|
||||
data_width = 64,
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
|
||||
self.add_csr("pcie_phy")
|
||||
|
||||
# Endpoint
|
||||
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
|
||||
|
||||
# Wishbone bridge
|
||||
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
|
||||
base_address = self.mem_map["csr"])
|
||||
self.add_wb_master(self.pcie_bridge.wishbone)
|
||||
|
||||
# DMA0
|
||||
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 1)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
self.add_csr("pcie_msi")
|
||||
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
|
||||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
self.add_constant(k + "_INTERRUPT", i)
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
self.submodules.leds = LedChaser(
|
||||
|
|
@ -139,7 +107,7 @@ def main():
|
|||
parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,10 @@ from litex.soc.cores.led import LedChaser
|
|||
from litedram.modules import MT8JTF12864
|
||||
from litedram.phy import s7ddrphy
|
||||
|
||||
|
||||
from litepcie.phy.s7pciephy import S7PCIEPHY
|
||||
from litepcie.software import generate_litepcie_software
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class _CRG(Module):
|
||||
|
|
@ -44,7 +48,7 @@ class _CRG(Module):
|
|||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
|
||||
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
|
||||
platform = vc707.Platform()
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
|
|
@ -73,6 +77,14 @@ class BaseSoC(SoCCore):
|
|||
l2_cache_reverse = True
|
||||
)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
self.add_csr("pcie_phy")
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
self.submodules.leds = LedChaser(
|
||||
pads = platform.request_all("user_led"),
|
||||
|
|
@ -85,14 +97,19 @@ def main():
|
|||
parser = argparse.ArgumentParser(description="LiteX SoC on VC707")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(**soc_sdram_argdict(args))
|
||||
soc = BaseSoC(with_pcie_=args.with_pcie, **soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
if args.driver:
|
||||
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
||||
|
|
|
|||
|
|
@ -24,9 +24,6 @@ from litedram.modules import MT40A512M8
|
|||
from litedram.phy import usddrphy
|
||||
|
||||
from litepcie.phy.usppciephy import USPPCIEPHY
|
||||
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
|
||||
from litepcie.frontend.dma import LitePCIeDMA
|
||||
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
|
||||
from litepcie.software import generate_litepcie_software
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
|
@ -95,41 +92,11 @@ class BaseSoC(SoCCore):
|
|||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
assert self.csr_data_width == 32
|
||||
# PHY
|
||||
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
|
||||
self.add_csr("pcie_phy")
|
||||
|
||||
# Endpoint
|
||||
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
|
||||
|
||||
# Wishbone bridge
|
||||
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
|
||||
base_address = self.mem_map["csr"])
|
||||
self.add_wb_master(self.pcie_bridge.wishbone)
|
||||
|
||||
# DMA0
|
||||
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 1)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
self.add_csr("pcie_msi")
|
||||
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
|
||||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
self.add_constant(k + "_INTERRUPT", i)
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
self.submodules.leds = LedChaser(
|
||||
|
|
|
|||
Loading…
Reference in New Issue