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targets/CRG: platforms are now automatically constraining the input clocks.

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This commit is contained in:
Florent Kermarrec 2020-05-05 11:51:57 +02:00
parent 1f88a9d5ec
commit 84468c2a63
19 changed files with 0 additions and 21 deletions
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1
litex_boards/targets/aller.py
View file

@ -48,7 +48,6 @@ class CRG(Module, AutoCSR):
# Clk/Rst
clk100 = platform.request("clk100")
platform.add_period_constraint(clk100, 1e9/100e6)
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6*sys_clk_freq))

1
litex_boards/targets/c10lprefkit.py
View file

@ -34,7 +34,6 @@ class _CRG(Module):
# Clk / Rst
clk12 = platform.request("clk12")
platform.add_period_constraint(clk12, 1e9/12e6)
# PLL
self.submodules.pll = pll = Cyclone10LPPLL(speedgrade="-A7")

1
litex_boards/targets/camlink_4k.py
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@ -37,7 +37,6 @@ class _CRG(Module):
# clk / rst
clk27 = platform.request("clk27")
platform.add_period_constraint(clk27, 1e9/27e6)
# power on reset
por_count = Signal(16, reset=2**16-1)

1
litex_boards/targets/colorlight_5a_75b.py
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@ -67,7 +67,6 @@ class _CRG(Module):
# Clk / Rst
clk25 = platform.request("clk25")
rst_n = 1 if not with_rst else platform.request("user_btn_n", 0)
platform.add_period_constraint(clk25, 1e9/25e6)
# PLL
self.submodules.pll = pll = ECP5PLL()

1
litex_boards/targets/de0nano.py
View file

@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")

1
litex_boards/targets/de10lite.py
View file

@ -34,7 +34,6 @@ class _CRG(Module):
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-7")

1
litex_boards/targets/de10nano.py
View file

@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
self.submodules.pll = pll = CycloneVPLL(speedgrade="-I7")

1
litex_boards/targets/de1soc.py
View file

@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")

1
litex_boards/targets/de2_115.py
View file

@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-7")

1
litex_boards/targets/ecp5_evn.py
View file

@ -25,7 +25,6 @@ class _CRG(Module):
# clk / rst
clk = clk12 = platform.request("clk12")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk12, 1e9/12e6)
if x5_clk_freq is not None:
clk = clk50 = platform.request("ext_clk50")
self.comb += platform.request("ext_clk50_en").eq(1)

1
litex_boards/targets/ecpix5.py
View file

@ -39,7 +39,6 @@ class _CRG(Module):
# Clk / Rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk100, 1e9/100e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)

1
litex_boards/targets/hadbadge.py
View file

@ -38,7 +38,6 @@ class _CRG(Module):
# Clk / Rst
clk8 = platform.request("clk8")
platform.add_period_constraint(clk8, 1e9/8e6)
# PLL
self.submodules.pll = pll = ECP5PLL()

3
litex_boards/targets/linsn_rv901t.py
View file

@ -32,7 +32,6 @@ class _CRG(Module):
# # #
clk25 = platform.request("clk25")
platform.add_period_constraint(clk25, 1e9/25e6)
self.submodules.pll = pll = S6PLL(speedgrade=-2)
pll.register_clkin(clk25, 25e6)
@ -96,8 +95,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,

1
litex_boards/targets/nereid.py
View file

@ -47,7 +47,6 @@ class CRG(Module, AutoCSR):
# Clk/Rst
clk100 = platform.request("clk100")
platform.add_period_constraint(clk100, 1e9/100e6)
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6*sys_clk_freq))

1
litex_boards/targets/orangecrab.py
View file

@ -38,7 +38,6 @@ class _CRG(Module):
# Clk / Rst
clk48 = platform.request("clk48")
platform.add_period_constraint(clk48, 1e9/48e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)

1
litex_boards/targets/tagus.py
View file

@ -46,7 +46,6 @@ class CRG(Module, AutoCSR):
# Clk/Rst
clk100 = platform.request("clk100")
platform.add_period_constraint(clk100, 1e9/100e6)
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6*sys_clk_freq))

1
litex_boards/targets/trellisboard.py
View file

@ -39,7 +39,6 @@ class _CRG(Module):
# Clk / Rst
clk12 = platform.request("clk12")
rst = platform.request("user_btn", 0)
platform.add_period_constraint(clk12, 1e9/12e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)

1
litex_boards/targets/ulx3s.py
View file

@ -36,7 +36,6 @@ class _CRG(Module):
# Clk / Rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
platform.add_period_constraint(clk25, 1e9/25e6)
# PLL
self.submodules.pll = pll = ECP5PLL()

1
litex_boards/targets/versa_ecp5.py
View file

@ -40,7 +40,6 @@ class _CRG(Module):
# Clk / Rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk100, 1e9/100e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)