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efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration...

This commit is contained in:
Florent Kermarrec 2021-11-10 19:40:35 +01:00
parent 224f527baa
commit 855fd7e3d7
2 changed files with 7 additions and 4 deletions
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5
litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py
View File

@ -14,7 +14,6 @@ from litex.build.efinix import EfinixProgrammer
_io = [
# Clk
("clk40", 0, Pins("P19"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
("clk50", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
# Leds
("user_led", 0, Pins("AB16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
@ -90,6 +89,10 @@ _io = [
Subsignal("mdio", Pins("D24")),
IOStandard("3.3_V_LVTTL_/_LVCMOS")
),
# DRAM.
("br0_pll_clkin", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
("br1_pll_clkin", 0, Pins("AA9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
]
# Connectors ---------------------------------------------------------------------------------------

6
litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
View File

@ -114,7 +114,7 @@ class BaseSoC(SoCCore):
if False:
# DRAM / PLL Blocks.
# ------------------
dram_clk = platform.request("clk50")
dram_clk = platform.request("br0_pll_clkin")
platform.toolchain.excluded_ios.append(dram_clk)
block = {"type" : "DRAM"}
@ -124,8 +124,8 @@ class BaseSoC(SoCCore):
# DRAM Rst.
# ---------
pll_dram_rstn = platform.add_iface_io("pll_dram_rstn")
self.comb += pll_dram_rstn.eq(platform.request("user_btn", 1))
br0_pll_rstn = platform.add_iface_io("br0_pll_rstn")
self.comb += br0_pll_rstn.eq(platform.request("user_btn", 1))
self.specials += Instance("ddr_reset_sequencer",
i_ddr_rstn_i = ~ResetSignal("sys"),
i_clk = ClockSignal("sys"),