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platform/hadbadge: cleanup/simplify and add copyrights

This commit is contained in:
Florent Kermarrec 2020-01-07 10:29:01 +01:00
parent 829898d652
commit 85c4f76eba
1 changed files with 137 additions and 133 deletions
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124
litex_boards/partner/platforms/hadbadge.py
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@ -1,3 +1,9 @@
# This file is Copyright (c) 2020 Michael Welling <mwelling@ieee.org>
# This file is Copyright (c) 2020 Sean Cross <sean@xobs.io>
# This file is Copyright (c) 2020 Drew Fustini <drew@pdp7.com>
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
@ -5,13 +11,17 @@ from litex.build.lattice import LatticePlatform
_io = [ _io = [
("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")), ("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")),
("programn", 0, Pins("R1"), IOStandard("LVCMOS33")), ("programn", 0, Pins("R1"), IOStandard("LVCMOS33")),
("serial", 0, ("serial", 0,
Subsignal("rx", Pins("U2"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")), Subsignal("rx", Pins("U2"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
Subsignal("tx", Pins("U1"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("U1"), IOStandard("LVCMOS33")),
), ),
("led", 0, Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"), IOStandard("LVCMOS33")), # Anodes ("led", 0, Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"), IOStandard("LVCMOS33")), # Anodes
("led", 1, Pins("P19 L18 K18"), IOStandard("LVCMOS33")), # Cathodes via FET ("led", 1, Pins("P19 L18 K18"), IOStandard("LVCMOS33")), # Cathodes via FET
("usb", 0, ("usb", 0,
Subsignal("d_p", Pins("F3")), Subsignal("d_p", Pins("F3")),
Subsignal("d_n", Pins("G3")), Subsignal("d_n", Pins("G3")),
@ -19,6 +29,7 @@ _io = [
Subsignal("vbusdet", Pins("F4")), Subsignal("vbusdet", Pins("F4")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
("keypad", 0, ("keypad", 0,
Subsignal("left", Pins("G2"), Misc("PULLMODE=UP")), Subsignal("left", Pins("G2"), Misc("PULLMODE=UP")),
Subsignal("right", Pins("F2"), Misc("PULLMODE=UP")), Subsignal("right", Pins("F2"), Misc("PULLMODE=UP")),
@ -29,6 +40,7 @@ _io = [
Subsignal("a", Pins("D1"), Misc("PULLMODE=UP")), Subsignal("a", Pins("D1"), Misc("PULLMODE=UP")),
Subsignal("b", Pins("E2"), Misc("PULLMODE=UP")), Subsignal("b", Pins("E2"), Misc("PULLMODE=UP")),
), ),
("hdmi_out", 0, ("hdmi_out", 0,
Subsignal("clk_p", Pins("P20"), Inverted(), IOStandard("TMDS_33")), Subsignal("clk_p", Pins("P20"), Inverted(), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("R20"), Inverted(), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("R20"), Inverted(), IOStandard("TMDS_33")),
@ -38,54 +50,71 @@ _io = [
Subsignal("data1_n", Pins("M20"), IOStandard("TMDS_33")), Subsignal("data1_n", Pins("M20"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("L16"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("L16"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("L17"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("L17"), IOStandard("TMDS_33")),
Subsignal("hpd_notif", Pins("R18"), IOStandard("LVCMOS33"), Inverted()), # Also called HDMI_HEAC_n Subsignal("hpd_notif", Pins("R18"), IOStandard("LVCMOS33")), # Also called HDMI_HEAC_n
Subsignal("hdmi_heac_p", Pins("T19"), IOStandard("LVCMOS33"), Inverted()), Subsignal("hdmi_heac_p", Pins("T19"), IOStandard("LVCMOS33")),
Misc("DRIVE=4"), Misc("DRIVE=4"),
), ),
("lcd", 0, ("lcd", 0,
Subsignal("db", Pins("J3 H1 K4 J1 K3 K2 L4 K1 L3 L2 M4 L1 M3 M1 N4 N2 N3 N1"), IOStandard("LVCMOS33")), Subsignal("db", Pins(
Subsignal("rd", Pins("P2"), IOStandard("LVCMOS33")), "J3 H1 K4 J1 K3 K2 L4 K1",
Subsignal("wr", Pins("P4"), IOStandard("LVCMOS33")), "L3 L2 M4 L1 M3 M1 N4 N2",
Subsignal("rs", Pins("P1"), IOStandard("LVCMOS33")), "N3 N1")),
Subsignal("cs", Pins("P3"), IOStandard("LVCMOS33")), Subsignal("rd", Pins("P2")),
Subsignal("id", Pins("J4"), IOStandard("LVCMOS33")), Subsignal("wr", Pins("P4")),
Subsignal("rst", Pins("H2"), IOStandard("LVCMOS33")), Subsignal("rs", Pins("P1")),
Subsignal("fmark", Pins("G1"), IOStandard("LVCMOS33")), Subsignal("cs", Pins("P3")),
Subsignal("blen", Pins("P5"), IOStandard("LVCMOS33")), Subsignal("id", Pins("J4")),
Subsignal("rst", Pins("H2")),
Subsignal("fmark", Pins("G1")),
Subsignal("blen", Pins("P5")),
IOStandard("LVCMOS33")
), ),
("spiflash", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")), ("spiflash", 0, # Clock needs to be accessed through USRMCLK
Subsignal("mosi", Pins("W2"), IOStandard("LVCMOS33")), Subsignal("cs_n", Pins("R2")),
Subsignal("miso", Pins("V2"), IOStandard("LVCMOS33")), Subsignal("mosi", Pins("W2")),
Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")), Subsignal("miso", Pins("V2")),
Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")), Subsignal("wp", Pins("Y2")),
Subsignal("hold", Pins("W1")),
IOStandard("LVCMOS33")
), ),
("spiflash4x", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")), ("spiflash4x", 0, # Clock needs to be accessed through USRMCLK
Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")), Subsignal("cs_n", Pins("R2")),
Subsignal("dq", Pins("W2 V2 Y2 W1")),
IOStandard("LVCMOS33")
), ),
("spiram4x", 0, ("spiram4x", 0,
Subsignal("cs_n", Pins("D20"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")), Subsignal("cs_n", Pins("D20")),
Subsignal("clk", Pins("E20"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")), Subsignal("clk", Pins("E20")),
Subsignal("dq", Pins("E19 D19 C20 F19"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP"), Misc("SLEWRATE=SLOW")), Subsignal("dq", Pins("E19 D19 C20 F19"), Misc("PULLMODE=UP")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")
), ),
("spiram4x", 1, ("spiram4x", 1,
Subsignal("cs_n", Pins("F20"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")), Subsignal("cs_n", Pins("F20")),
Subsignal("clk", Pins("J19"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")), Subsignal("clk", Pins("J19")),
Subsignal("dq", Pins("J20 G19 G20 H20"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP"), Misc("SLEWRATE=SLOW")), Subsignal("dq", Pins("J20 G19 G20 H20"), Misc("PULLMODE=UP")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")
), ),
("sao", 0, ("sao", 0,
Subsignal("sda", Pins("B3")), Subsignal("sda", Pins("B3")),
Subsignal("scl", Pins("B2")), Subsignal("scl", Pins("B2")),
Subsignal("gpio", Pins("A2 A3 B4")), Subsignal("gpio", Pins("A2 A3 B4")),
Subsignal("drm", Pins("A4")), Subsignal("drm", Pins("A4")),
IOStandard("LVCMOS33"),
), ),
("sao", 1, ("sao", 1,
Subsignal("sda", Pins("A16")), Subsignal("sda", Pins("A16")),
Subsignal("scl", Pins("B17")), Subsignal("scl", Pins("B17")),
Subsignal("gpio", Pins("B18 A17 B16")), Subsignal("gpio", Pins("B18 A17 B16")),
Subsignal("drm", Pins("C17")), Subsignal("drm", Pins("C17")),
IOStandard("LVCMOS33"),
), ),
("testpts", 0, ("testpts", 0,
Subsignal("a1", Pins("A15")), Subsignal("a1", Pins("A15")),
Subsignal("a2", Pins("C16")), Subsignal("a2", Pins("C16")),
@ -95,22 +124,9 @@ _io = [
Subsignal("b2", Pins("C15")), Subsignal("b2", Pins("C15")),
Subsignal("b3", Pins("A13")), Subsignal("b3", Pins("A13")),
Subsignal("b4", Pins("B13")), Subsignal("b4", Pins("B13")),
IOStandard("LVCMOS33"),
), ),
# rev a
# ("sdram_clock", 0, Pins("C11"), IOStandard("LVCMOS33")),
# ("sdram", 0,
# Subsignal("a", Pins("D10 C10 B10 A10 C14 E17 A12 B12 H17 G18 A9 A11 A7")),
# Subsignal("dq", Pins("C5 A5 B6 D6 B5 C6 A6 C7")),
# Subsignal("we_n", Pins("C8")),
# Subsignal("ras_n", Pins("A8")),
# Subsignal("cas_n", Pins("B8")),
# Subsignal("cs_n", Pins("D9")),
# Subsignal("cke", Pins("B11")),
# Subsignal("ba", Pins("C9 B9")),
# Subsignal("dm", Pins("D11")),
# IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
# ),
# rev b
("sdram_clock", 0, Pins("D11"), IOStandard("LVCMOS33")), ("sdram_clock", 0, Pins("D11"), IOStandard("LVCMOS33")),
("sdram", 0, ("sdram", 0,
Subsignal("a", Pins("A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11")), Subsignal("a", Pins("A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11")),
@ -124,27 +140,14 @@ _io = [
Subsignal("dm", Pins("A10")), Subsignal("dm", Pins("A10")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST") IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
), ),
# Only used for simulation
("wishbone", 0,
Subsignal("adr", Pins(30)),
Subsignal("dat_r", Pins(32)),
Subsignal("dat_w", Pins(32)),
Subsignal("sel", Pins(4)),
Subsignal("cyc", Pins(1)),
Subsignal("stb", Pins(1)),
Subsignal("ack", Pins(1)),
Subsignal("we", Pins(1)),
Subsignal("cti", Pins(3)),
Subsignal("bte", Pins(2)),
Subsignal("err", Pins(1))
),
("reset", 0, Pins(1), IOStandard("LVCMOS33")),
] ]
_connectors = [ _connectors = [
("pmod", "A15 C16 A14 D16 B15 C15 A13 B13"), ("pmod", "A15 C16 A14 D16 B15 C15 A13 B13"),
("genio", "C5 B5 A5 C6 B6 A6 D6 C7 A7 C8 B8 A8 D9 C9 B9 A9 D10 C10 B10 A10 D11 C11 B11 A11 G18 H17 B12 A12 E17 C14"), ("genio", "C5 B5 A5 C6 B6 A6 D6 C7 ", # 0-7
"A7 C8 B8 A8 D9 C9 B9 A9 ", # 8-15
"D10 C10 B10 A10 D11 C11 B11 A11", # 16-23
"G18 H17 B12 A12 E17 C14"), # 24-29
] ]
_pmod_gpio = [ _pmod_gpio = [
@ -204,8 +207,9 @@ class Platform(LatticePlatform):
default_clk_name = "clk8" default_clk_name = "clk8"
default_clk_period = 1e9/8e6 default_clk_period = 1e9/8e6
def __init__(self, device="LFE5U-45F", **kwargs): def __init__(self, toolchain="trellis", **kwargs):
LatticePlatform.__init__(self, device + "-CABGA381", io=_io, connectors=_connectors, toolchain="trellis", **kwargs) LatticePlatform.__init__(self, "LFE5U-45F-CABGA381", io=_io, connectors=_connectors,
toolchain=toolchain, **kwargs)
def create_programmer(self): def create_programmer(self):
raise ValueError("{} programmer is not supported" raise ValueError("{} programmer is not supported"