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targets: Fix --bios-flash-offset support and other minor cleanups.

This commit is contained in:
Florent Kermarrec 2021-12-20 21:41:12 +01:00
parent c6303480cb
commit 8664b59f23
10 changed files with 32 additions and 34 deletions
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4
litex_boards/targets/1bitsquared_icebreaker.py
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@ -145,14 +145,14 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream") parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)") parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)")
parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)") parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash (default: 0x40000)")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (with DVI PMOD)") parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (with DVI PMOD)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal, with_video_terminal = args.with_video_terminal,
**soc_core_argdict(args) **soc_core_argdict(args)

4
litex_boards/targets/1bitsquared_icebreaker_bitsy.py
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@ -119,14 +119,14 @@ def main():
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream and bios") parser.add_argument("--flash", action="store_true", help="Flash bitstream and bios")
parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)") parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)")
parser.add_argument("--bios-flash-offset", default=0xa0000, help="BIOS offset in SPI Flash (default: 0xa0000)") parser.add_argument("--bios-flash-offset", default="0xa0000", help="BIOS offset in SPI Flash (default: 0xa0000)")
parser.add_argument("--revision", default="v1", help="Board revision 'v0' or 'v1'") parser.add_argument("--revision", default="v1", help="Board revision 'v0' or 'v1'")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
revision = args.revision, revision = args.revision,
**soc_core_argdict(args) **soc_core_argdict(args)

12
litex_boards/targets/efinix_xyloni_dev_kit.py
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@ -88,18 +88,18 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Xyloni Dev Kit") parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Xyloni Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream") parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
parser.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency (default: 33.333MHz)") parser.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency (default: 33.333MHz)")
parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)") parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash (default: 0x40000)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)) **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))

12
litex_boards/targets/jungle_electronics_fireant.py
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@ -103,18 +103,18 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Jungle Electronics FireAnt") parser = argparse.ArgumentParser(description="LiteX SoC on Jungle Electronics FireAnt")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream") parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
parser.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency (default: 33.333MHz)") parser.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency (default: 33.333MHz)")
parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)") parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash (default: 0x40000)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)) **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))

6
litex_boards/targets/kosagi_fomu.py
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@ -170,7 +170,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Fomu") parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)") parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)")
parser.add_argument("--bios-flash-offset", default=0x20000, help="BIOS offset in SPI Flash (default: 0x20000)") parser.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash (default: 0x20000)")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream") parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
@ -179,7 +179,7 @@ def main():
dfu_flash_offset = 0x40000 dfu_flash_offset = 0x40000
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = dfu_flash_offset + args.bios_flash_offset, bios_flash_offset = dfu_flash_offset + int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
) )
@ -187,7 +187,7 @@ def main():
builder.build(run=args.build) builder.build(run=args.build)
if args.flash: if args.flash:
flash(builder.output_dir, soc.build_name, args.bios_flash_offset) flash(builder.output_dir, soc.build_name, int(args.bios_flash_offset, 0))
if __name__ == "__main__": if __name__ == "__main__":
main() main()

4
litex_boards/targets/lattice_ice40up5k_evn.py
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@ -149,14 +149,14 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Lattice iCE40UP5k EVN breakout board") parser = argparse.ArgumentParser(description="LiteX SoC on Lattice iCE40UP5k EVN breakout board")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)") parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)")
parser.add_argument("--bios-flash-offset", default=0x20000, help="BIOS offset in SPI Flash (default: 0x20000)") parser.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash (default: 0x20000)")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream") parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
) )

6
litex_boards/targets/muselab_icesugar.py
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@ -118,13 +118,13 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream") parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)") parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)")
parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)") parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash (default: 0x40000)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
) )
@ -136,7 +136,7 @@ def main():
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin")) prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
if args.flash: if args.flash:
flash(args.bios_flash_offset) flash(int(args.bios_flash_offset, 0))
if __name__ == "__main__": if __name__ == "__main__":
main() main()

8
litex_boards/targets/qwertyembedded_beaglewire.py
View File

@ -78,7 +78,7 @@ class BaseSoC(SoCCore):
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Beaglewire", ident = "LiteX SoC on Beaglewire",
ident_version = True, ident_version = True,
**kwargs) **kwargs)
@ -115,16 +115,14 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Beaglewire") parser = argparse.ArgumentParser(description="LiteX SoC on Beaglewire")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash (default: 0x60000)") parser.add_argument("--bios-flash-offset", default="0x60000", help="BIOS offset in SPI Flash (default: 0x60000)")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--output_dir", default="build", help="Output directory of csr")
parser.add_argument("--csr_csv", default="build/csr.csv", help="csr.csv")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
) )

4
litex_boards/targets/tinyfpga_bx.py
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@ -69,14 +69,14 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on TinyFPGA BX") parser = argparse.ArgumentParser(description="LiteX SoC on TinyFPGA BX")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--bios-flash-offset", default=0x50000, help="BIOS offset in SPI Flash (default: 0x50000)") parser.add_argument("--bios-flash-offset", default="0x50000", help="BIOS offset in SPI Flash (default: 0x50000)")
parser.add_argument("--sys-clk-freq", default=16e6, help="System clock frequency (default: 16MHz)") parser.add_argument("--sys-clk-freq", default=16e6, help="System clock frequency (default: 16MHz)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
) )

6
litex_boards/targets/trenz_tec0117.py
View File

@ -160,7 +160,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on TEC0117") parser = argparse.ArgumentParser(description="LiteX SoC on TEC0117")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--bios-flash-offset", default=0x0000, help="BIOS offset in SPI Flash (0x00000 default)") parser.add_argument("--bios-flash-offset", default="0x0000", help="BIOS offset in SPI Flash (0x00000 default)")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS") parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS")
parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 25MHz)") parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 25MHz)")
sdopts = parser.add_mutually_exclusive_group() sdopts = parser.add_mutually_exclusive_group()
@ -171,7 +171,7 @@ def main():
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = args.bios_flash_offset, bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
) )
@ -191,7 +191,7 @@ def main():
if args.flash: if args.flash:
prog = soc.platform.create_programmer() prog = soc.platform.create_programmer()
prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs")) prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
flash(args.bios_flash_offset) flash(int(args.bios_flash_offset, 0))
if __name__ == "__main__": if __name__ == "__main__":
main() main()