efinix_trion_t120_bga576_dev_kit: Remove test command.
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@ -112,8 +112,6 @@ class BaseSoC(SoCCore):
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# LPDDR3 SDRAM -----------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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#./efinix_trion_t120_bga576_dev_kit.py --with-lpddr3 --sys-clk-freq=50e6 --csr-csv=csr.csv --build --load
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# DRAM / PLL Blocks.
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# ------------------
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br0_pll_clkin = platform.request("br0_pll_clkin")
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