Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets: Fix typos.

This commit is contained in:
Florent Kermarrec 2022-04-21 12:29:54 +02:00
parent a611f035d6
commit 88f2625c3d
3 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex_boards/targets/digilent_arty.py
View File

@ -74,7 +74,7 @@ class BaseSoC(SoCCore):
platform = arty.Platform(variant=variant, toolchain=toolchain) platform = arty.Platform(variant=variant, toolchain=toolchain)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
with_dram = (kwargs.get("integrated_main_ram_size", 0) != 0) with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
self.submodules.crg = _CRG(platform, sys_clk_freq, with_dram) self.submodules.crg = _CRG(platform, sys_clk_freq, with_dram)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------

4
litex_boards/targets/gsd_orangecrab.py
View File

@ -149,12 +149,12 @@ class BaseSoC(SoCCore):
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" with_usb_pll = kwargs.get("uart_name") in ["serial", "usb_acm"]
crg_cls = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG crg_cls = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll) self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
if kwargs["uart_name"] in ["serial", "usb_acm"]: if kwargs["uart_name"] in ["serial"]:
kwargs["uart_name"] = "usb_acm" kwargs["uart_name"] = "usb_acm"
# Defaults to USB ACM through ValentyUSB. # Defaults to USB ACM through ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")

1
litex_boards/targets/sipeed_tang_nano.py
View File

@ -68,6 +68,7 @@ class BaseSoC(SoCMini):
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCMini ---------------------------------------------------------------------------------- # SoCMini ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
SoCMini.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Nano", **kwargs) SoCMini.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Nano", **kwargs)
# UARTBone --------------------------------------------------------------------------------- # UARTBone ---------------------------------------------------------------------------------