isx_im1283: connect CRG reset to PLL

This fixes soft reset.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

litex_boards/targets/isx_im1283.py

@@ -39,10 +39,12 @@ class _CRG(LiteXModule):
         # # #
         self.pll = pll = S7PLL(speedgrade=-2)
         pll.register_clkin(platform.request("clk200"), 200e6)
+        self.comb += pll.reset.eq(self.rst)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)